Microprocessor And Assembly Language MCQ 03

1.      BIU STAND FOR:

a.      Bus interface unit

b.      Bess interface unit

c.       A and B

d.      None of these

2.      EU STAND FOR:

a.      Execution unit

b.      Execute unit

c.       Exchange unit

d.      None of these

3.      The register can be divided are:

a.       3

b.      4

c.       5

d.      6

4.      Which are the part of architecture of 8086:

a.       The bus interface unit

b.      The execution unit

c.       Both A and B

d.      None of these

5.      Which are the four categories of registers:

a.       General- purpose register

b.      Pointer or index registers

c.       Segment registers

d.      Other register

e.      All of these

6.      Eight of the register are known as:

a.      General- purpose register

b.      Pointer or index registers

c.       Segment registers

d.      Other register

7.      The four index register can be used for:

a.      Arithmetic operation

b.      Multipulation operation

c.       Subtraction operation

d.      All of these

8.      IP Stand for:

a.      Instruction pointer

b.      Instruction purpose

c.       Instruction paints

d.      None of these

9.      CS Stand for:

a.      Code segment

b.      Coot segment

c.       Cost segment

d.      Counter segment

10.  DS Stand for:

a.      Data segment

b.      Direct segment

c.       Declare segment

d.      Divide segment

11.  Which are the segment:

a.       CS: Code segment

b.      DS: data segment

c.       SS: Stack segment

d.      ES:extra segment

e.      All of these

12.  The acculatator is 16 bit wide and is called:

a.      AX

b.      AH

c.       AL

d.      DL

13.  The upper 8 bit are called______:

a.       BH

b.      BL

c.       AH

d.      CH

14.  The lower 8 bit are called_______:

a.      AL

b.      CL

c.       BL

d.      DL

15.  IP stand for:

a.       Industry pointer

b.      Instruction pointer 

c.       Index pointer

d.      None of these

16.  Which has great important in modular programming:

a.      Stack segment

b.      Queue segment

c.       Array segment

d.      All of these

17.  Which register containing the 8086/8088 flag:

a.      Status register

b.      Stack register

c.       Flag register

d.      Stand register

18.  Which flag are used to record specific characteristics of arithmetic and logical instructions:

a.       The stack

b.      The stand

c.       The status

d.      The queue

19.  How many bits the instruction pointer is wide:

a.      16 bit

b.      32 bit

c.       64 bit

d.      128 bit

20.  How many type of addressing in memory:

a.       Logical address

b.      Physical address

c.       Both A and B

d.      None of these

21.  The size of each segment in 8086 is:

a.      64 kb

b.      24 kb

c.       50 kb

d.      16kb

22.  The physical address of memory is :

a.      20 bit

b.      16 bit

c.       32 bit

d.      64 bit

23.  The _______ address of a memory is a 20 bit address for the 8086 microprocessor:

a.      Physical

b.      Logical

c.       Both

d.      None of these

24.  To provide clarity in case of the status register_______ and __________ placeholders are displayed:

a.       Binary

b.      Hexadecimal

c.       Both

d.      None of these

25.  The pin configuration of 8086 is available in the________:

a.      40 pin

b.      50 pin

c.       30 pin

d.      20 pin

26.  DIP stand for:

a.       Deal inline package

b.      Dual inline package

c.       Direct inline package

d.      Digital inline package

27.  PA stand for:

a.       Project address

b.      Physical address

c.       Pin address

d.      Pointer address

28.  SBA stand for:

a.       Segment bus address

b.      Segment bit address

c.       Segment base address

d.      Segment byte address

29.  EA stand for:

a.      Effective address

b.      Electrical address

c.       Effect address

d.      None of these

30.  BP stand for:

a.       Bit pointer

b.      Base pointer

c.       Bus pointer

d.      Byte pointer

31.  DI stand for:

a.      Destination index

b.      Defect index

c.       Definition index

d.      Delete index

32.  SI stand for:

a.       Stand index

b.      Source index

c.       Segment index

d.      Simple index

33.  DS stand for:

a.      Default segment

b.      Defect segment

c.       Delete segment

d.      Definition segment

34.  ALE stand for:

a.      Address latch enable

b.      Address light enable

c.       Address lower enable

d.      Address last enable

35.  AD stand for:

a.      Address data

b.      Address delete

c.       Address date

d.      Address deal

36.   NMI stand for:

a.      Non mask able interrupt

b.      Non mistake interrupt

c.       Both

d.      None of these

37.    PC stand for:

a.      program counter

b.      project counter

c.        protect counter

d.      planning counter

38.  AH stand for:

a.      Accumulator high

b.      Address high

c.       Appropriate high

d.      Application high

39.  AL stand for:

a.      Accumulator low

b.      Address low

c.       Appropriate low

d.      Application low

40.  Which are the categorized of flag:

a.       Conditional flag

b.      Control flag

c.       Both a and b

d.      None of these

41.  Which are the general register:

a.       AX: Accumulator

b.      BX: Base

c.       CX: Count

d.      DX: Data

e.      All of these

42.  ________ is the most important segment and it contains the actual assembly language instruction to be executed by the microprocessor:

a.       Data segment

b.      Code segment

c.       Stack segment

d.      Extra segment

43.  The offset of a particular segment varies from _________:

a.       000H to FFFH

b.      0000H to FFFFH

c.       00H to FFH

d.      00000H to FFFFFH

44.  Which are the factor of cache memory:

a.       Architecture of the microprocessor

b.      Properties of the programs being executed

c.       Size organization of the cache

d.      All of these

45.  ________ is usually the first level of memory access by the microprocessor:

a.      Cache memory

b.      Data memory

c.       Main memory

d.      All of these

46.  which is the small amount of high- speed memory used to work directly with the microprocessor:

a.      Cache

b.      Case

c.       Cost

d.      Coos

47.  The cache usually gets its data from the_________ whenever the instruction or data is required by the CPU:

a.      Main memory

b.      Case memory

c.       Cache memory

d.      All of these

48.  The amount of information which can be placed at one time in the cache memory is called_________:

a.       Circle size

b.      Line size

c.       Wide line size

d.      None of these

49.  How many type of cache memory:

a.       1

b.      2

c.       3

d.      4

50.  Which is the type of cache memory:

a.       Fully associative cache

b.      Direct-mapped cache

c.       Set-associative cache

d.      All of these

51.  Which memory is used to holds the address of the data stored in the cache :

a.      Associative memory

b.      Case memory

c.       Ordinary memory

d.      None of these

52.    Direct mapping is a _________ to implement cache memory :

a.      Cheaper way

b.      Case way

c.       Cache way

d.      None of these

53.  A fourth bit called the _________:

a.       Direct bit

b.      Cache bit

c.       Valid bit

d.      All of these

54.  FIFO stand for:

a.       First in first other

b.      First in first out

c.       First in first over

d.      None of these

55.  Microprocessor reference that are available in the cache are called______:

a.      Cache hits

b.      Cache line

c.       Cache memory

d.      All of these

56.  Microprocessor reference that are not available in the cache are called_________:

a.       Cache hits

b.      Cache line

c.       Cache misses

d.      Cache memory

57.  __________ is the most commonly used cache controller with a number of processor sets:

a.       L211 controller

b.      L210 controller

c.       L214 controller

d.      None of these

58.  LFB stand for:

a.       Line full buffers

b.      Line fill buffers

c.       Line fan buffers

d.      None of these

59.  LRB stand for:

a.      Line read buffers

b.      Line ready buffers

c.       Line root buffers

d.      Line right buffers

60.  EB stand for:

a.       Effect buffers

b.      Effecting buffers

c.       Effection buffers

d.      None of these

61.    EB stand for:

a.       Effect buffers

b.      Effecting buffers

c.       Effection buffers

d.      Eviction buffers

62.  WB stand for:

a.      Write buffers

b.      Written buffers

c.       Wrote buffers

d.      None of these

63.  WA stand for:

a.      Write allocate

b.      Wrote allocate

c.       Way allocate

d.      Word allocate

64.  In case of direct- mapped cache lower order line address bits are used the access the ___________:

a.       RAM

b.       ROM

c.       Directory

d.      HDD

65.   The index high order bits in the address known as_________:

a.      tags

b.      label

c.       point

d.      location

e.        

66.  The parity bits are used to check that a__________:

a.       Two bit error

b.      Single bit error

c.       Multi bit error

d.      None of these

67.   Who works as cache on the variable:

a.      Register

b.      Memory

c.       Pointer

d.      Segment

68.  Second level is a cache on the ________:

a.       Main memory

b.      RAM

c.       Both

d.      None of these

69.  The memory system is said to be effective if the access time of the cache is close to the effective access time of the_____:

a.       ROM

b.      RAM

c.       HDD

d.      Processor

70.  Cache is usually the____________ of memory access by the microprocessor:

a.      First level

b.      Second level

c.       Third level

d.      Fourth level

71.  The principal of working of the cache memory largely depends on which locality:

a.       Spatial locality

b.      Temporal locality

c.       Sequentially

d.      All of these

72.  Who work as a cache for the page table:

a.      TLB

b.      TLP

c.       LEB

d.      WAB

73.  Which formula is used to calculate the number of read stall cycles:

a.      Reads* Read miss rate * Read miss penalty

b.      Write* (Write miss rate * Write miss penalty)+write buffer stalls

c.        Memory access * Cache miss rate * Cache miss penalty

d.      None of these

74.  Which formula is used to calculate the number of write stall cycles:

a.       Reads* Read miss rate * Read miss penalty

b.      Write* (Write miss rate * Write miss penalty)+write buffer stalls

c.        Memory access * Cache miss rate * Cache miss penalty

d.      None of these

75.  Which formula is used to calculate the number of memory stall cycles:

a.       Reads* Read miss rate * Read miss penalty

b.      Write* (Write miss rate * Write miss penalty)+write buffer stalls

c.        Memory access * Cache miss rate * Cache miss penalty

d.      None of these

76.  Which causes the microprocessor to immediately terminate its present activity:

a.      RESET signal

b.      INTERUPT signal

c.       Both

d.      None of these

77.  Which are the cache controller ports:

a.       64-bit AHB-Lite slave ports

b.      64-bit AHB-Lite master ports

c.       Both

d.      None of these

78.   Cache can be controlled __________:

a.      16KB-2MB

b.      17 KB-2MB

c.       18 KB-2MB

d.      19 KB-2MB

79.  Which is responsible for all the outside world communication by the microprocessor:

a.      BIU

b.      PIU

c.       TIU

d.      LIU

e.        

80.  INTR: it implies the__________ signal:

a.      INTRRUPT REQUEST

b.      INTRRUPT RIGHT

c.       INTRRUPT RONGH

d.      INTRRUPT RESET