Sunday, 18 March 2012

Computer System Architecture MCQ 06


1.      Which is an important data transfer technique :

a.       CPU
b.      DMA
c.       CAD
d.      None of these

2.      Which device can be thought of as transducers which can sense physical effects and convert them into machine-tractable data:

a.       Storage devices
b.      Peripheral devices
c.       Both
d.      None

3.      Which devices are usually designed on the complex electromechanical principle:

a.       Storage devices
b.      Peripheral devices
c.       Input devices
d.      All of these

4.         Which disk is one of the important I/O devices and its most commonly used as permanent storage devices in any processor:

a.       Hard disk
b.      Optical disk
c.       Magneto disk
d.      Magneto Optical disk

5.      In storage devices PC have hard disk having capacities in the range of _____:

a.       12GB to 15GB
b.      15GB to 20GB
c.       20GB to 80GB
d.      80GB to 85GB

6.      Which disk is a 3.5-inch diskette with a capacity of 1.44MB:

a.       Soft disk
b.      Floppy disk
c.       Both
d.      None

7.      Which has a large storage capacity of 2 to8GB:

a.       Magnetic tape
b.      Magnetic disk
c.       Soft disk
d.      Floppy disk

8.      Which disk read the data by reflecting pulses of laser beams on the surface:

a.       Magnetic disk
b.      Soft disk
c.       Floppy disk
d.      Optical disk

9.      Data access time of optical disk varies from 200 to 350minutes with transfer rate of ________:
a.       130KB/s  to 400KB/s
b.      130KB/s  to 500KB/s
c.       150KB/s  to 600KB/s
d.      150KB/s  to 800KB/s
10.  NAND type flash memory data storage devices integrated with a _______ interface:

a.       ATM
b.      LAN
c.       USB
d.      DBMS

11.  Which disk is based on the same principle as the optical disk:

a.       Optical disk
b.      Magnetic disk
c.       Magneto-optical disk
d.      All of these

12.  WAN stands for:

a.       Wide area network
b.      Word area network
c.       World area network
d.      Window area network

13.   The human-interactive I/O devices can be further categorized as____:

a.       Direct
b.      Indirect
c.       Both
d.      None

14.  I/O devices are categorized in 2 parts are:

a.       Character devices
b.      Block devices
c.       Numeral devices
d.      Both a & b

15.  UART stands for:
a.       Universal asynchronization receiver/transmitter
b.      Universal asynchronous receiver/transmitter
c.       United asynchronous receiver/transmitter
d.      Universal automatic receiver/transmitter
16.  Which are following pointing devices:

a.       Light pen
b.      Joystick
c.       Mouse
d.      All of these

17.  Full form of LED:
a.       Light emitting diode
b.      Light encounter destination
c.       Live emitting diode
d.      None of these
18.   In_______ mouse we use pair of LED:

a.       Optical
b.      Digital
c.       Analog
d.      All of these

19.  ______is device that is designed for gaming purposes and based on principle of electricity:

a.       Joy
b.      Stick
c.       Joystick
d.      None of these

20.  Joystick uses shaft potentiometers for:

a.       X-Y DIRECTION
b.      Only X direction
c.       Only Y direction
d.      All of these

21.  Full form of ADC:
a.       Analog to digital converter
b.      Digital to analog converter
c.       Accumulator digital converter
d.      All of these
22.  A system that enables computer to recognize human voice called:

a.       Voice system
b.      Voice input system
c.       Input system
d.      None of these

23.  2 commonly used voice input systems are:

a.       Micro
b.      Microphone
c.       Voice recognition software
d.      Both b & c

24.  Optical scanner devices are:

a.       MICR
b.      OMR
c.       OCR
d.      All of these

25.  MICR stands for:
a.       Magnetic ink character recognition
b.      Magnetic initiate character recognition
c.       Both a & b
d.      None of these
26.  _______technique is used in evaluating  objective answer sheets:

a.       Optical Mark Reader
b.      Optical Marker Reader
c.       Optical Marker Reading
d.      All of these

27.  _______technique help in banking sector:

a.       OCR
b.      OMR
c.       MICR
d.      None of these

28.  ______camera records image, converts it into digital format via ADC and stores it on a frame buffer:

a.       Video
b.      Without video
c.       Audio
d.      None of these

29.  Sensors are______ type of devices:

a.       Interactive
b.      Non-interactive
c.       Interaction
d.      Intermediate

30.  Output devices commonly referred as:

a.       Terminals
b.      Host
c.       Receivers
d.      Senders

31.  Terminals classified in to 2 types are:

a.       Hard copy
b.      Soft copy
c.       Both a & b
d.      None of these

32.  VDU stands for:

a.       Video display unit
b.      Visual display unit
c.       Visual data unit
d.      None of these

33.   A monitor consists of :

a.       ARU
b.      BRT
c.       CRT
d.      ARU

34.  LCD stands for:
a.       Liquid crystal display
b.      Liquid catalog display
c.       Liquid crystal data
d.      Liquid code display
35.  The size of monitor ranges from:

a.       12-12 inch
b.      12-21 inch
c.       21-12 inch
d.      21-11 inch

36.  Range of color depends on:
a.        Number of bits code lines with each pixel
b.      Number of bits associated with each pixel
c.       Number of instructions associated with each pixel
d.      Number of code associated with each pixel
37.  Which parameter defines number of times electron beam scans screen in a second:

a.       Refresh rate
b.      Data transfer rate
c.       Pitch rate
d.      All of these

38.  Refresh rate refresh screen up to:

a.       30 Hz per frame
b.      33 Hz per frame
c.       44 Hz per frame
d.      20 Hz per frame

39.  Printer speed is ______pages per minute:

a.       13
b.      12
c.       11
d.      10

40.  Printer is a:

a.       Hardcopy
b.      Softcopy
c.       Both a & b
d.      None of these

41.  Laser printer is type of:

a.       Impact printer
b.      Non-impact printer
c.       Both a & b
d.      None of these

42.  ______printer print 120 to 200 characters per second:

a.       Dot-matrix
b.      Laser
c.       Line
d.      None of these

43.  In_______ printing, each character is printed on the paper by striking a pin or hammer against an inked ribbon:

a.       Non-impact printing
b.      Impact printing
c.       Both a & b
d.      None of these

44.  Dot matrix printer is 2 types is:

a.       Daisy wheels
b.      Matrix printer
c.       High quality matrix printer
d.      Both a & c

45.  In daisy wheel printer can print 40 character/second and bold characters are achieved by overprinting the text:

a.       Four times
b.      Double
c.       Once
d.      Thrice

46.     _______printers spray tiny droplets of coloured inks on the paper and pattern depends on how nozzle sprays the ink:

a.       Inkjet printer
b.      Laser printer
c.       Daisy wheel
d.      Dot matrix printer

47.  Laser printer is a type of :   

a.       Impact printing
b.      Non-impact printing
c.       Both a & b
d.      None of these

48.  ______are used for printing big charts, drawings, maps and 3 dimensional illustrations specially for architectural and designing purposes:

a.       Printers
b.      Plotters
c.       Speakers
d.      Mouse

49.  DAC stands for:
a.       Digital to analog converter
b.      Analog to digital converter
c.       Only digital converter
d.      Only analog converter
50.    In text to speech, speech is synthesized using lookup table of______ and these clubbed together to form_______:

a.       Phonemes, Words
b.      Phonemes, Sentences
c.       Character, Phonemes
d.      Word, Character

51.  ______interface is an entity  that controls data transfer from external device, main memory and or CPU registers:

a.       I/O interface
b.      CPU interface
c.       Input interface
d.      Output interface

52.  The operating mode of  I/O devices is_______ for different device:

a.       Same
b.      Different
c.       Optimum
d.      Medium

53.  To resolve problems of I/O devices there is a special hardware component between CPU and_______ to supervise and synchronize all input output transfers:

a.       Software
b.      Hardware
c.       Peripheral
d.      None of these

54.  I/O modules are designed with aims to:
a.       Achieve device independence
b.      Handle errors
c.       Speed up transfer of data
d.      Handle deadlocks
e.       Enable multi-user systems to use dedicated device
f.        All of these
55.  IDE is a_________ controller:

a.       Disk
b.      Floppy
c.       Hard
d.      None of these

56.  In devices, controller is used for______:

a.       Buffering the data
b.      Manipulate the data
c.       Calculate the data
d.      Input the data

57.  By which signal flow of traffic between internal and external devices is done:
a.       Only control signal
b.      Only timing signal
c.       Control and timing signal
d.      None of these
58.  In devices 2 status reporting signals are:

a.       BUSY
b.      READY
c.       Both a & b
d.      None of these

59.  I/O module must recognize a______ address for each peripheral it controls:

a.       Long
b.      Same
c.       Unique
d.      Bigger

60.  Each interaction b/w CPU and I/O module involves:

a.       Bus arbitration
b.      Bus revolution
c.       Data bus
d.      Control signals

61.  Which are 4 types of commands received by an interface:
a.       Control, status, data output, data input
b.      Only data input
c.       Control, flag, data output, address arbitration
d.      Data input, data output, status bit, decoder
62.  Two ways in which computer buses can communicate with memory in case of I/O devices by using:
a.       Separate buses for memory and I/O device
b.      Common bus for memory and I/O device
c.       both a & b
d.      none of these
63.  There are 2 ways in which addressing can be done in memory and I/O device:

a.       Isolated  I/O
b.      Memory-mapped I/O
c.       Both a & b
d.      None of these

64.  Advantages of isolated I/O are:
a.       Commonly usable
b.      Small number of I/O instructions
c.       Both a & b
d.      None of these
65.  In _______ addressing technique separate address space is used for both memory and I/O device:

a.       Memory-mapped I/O
b.      Isolated I/O
c.       Both a & b
d.      None of these

66.    _______is a single address space for storing both memory and I/O devices:

a.       Memory-mapped I/O
b.      Isolated I/O
c.       Separate I/O
d.      Optimum I/O

67.  Following are the disadvantages of memory-mapped I/O are:
a.       Valuable memory address space used up
b.      I/O module register treated as memory addresses
c.       Same machine intersection used to access both memory and I/O device
d.      All of these
68.  Who determine the address of I/O interface:

a.       Register select
b.      Chip select
c.       Both a & b
d.      None of these

69.  2 control lines in I/O interface is:

a.       RD, WR
b.      RD,DATA
c.       WR, DATA
d.      RD, MEMORY

70.  In I/O interface RS1 and RS0 are used for selecting:

a.       Memory
b.      Register
c.       CPU
d.      Buffer

71.  If CPU and I/O interface share a common bus than transfer of data b/w 2 units is said to be:

a.       Synchronous
b.      Asynchronous
c.       Clock dependent
d.      Decoder independent

72.  All the operations in a digital system are synchronized by a clock that is generated by:

a.       Clock
b.      Pulse
c.       Pulse generator
d.      Bus

73.  Asynchronous means:
a.       Not in step with the elapse of address
b.      Not in step with the elapse of control
c.       Not in step with the elapse of data
d.      Not in step with the elapse of time
74.  ________is a single control line that informs destination unit that a valid is available on the bus:

a.       Strobe
b.      Handshaking
c.       Synchronous
d.      Asynchronous

75.  What is disadvantage of strobe scheme:
a.       No surety that destination received data before source removes it
b.      Destination unit transfer without knowing whether source placed data on data bus
c.       Can’t said
d.      Both a & b
76.  In_______ technique has 1 or more control signal for acknowledgement that is used for intimation:

a.       Handshaking
b.      Strobe
c.       Both a & b
d.      None of these

77.  The keyboard has a__________ asynchronous transfer mode:

a.       Parallel
b.      Serial
c.       Optimum
d.      None

78.  In _______transfer each bit is sent one after the another in a sequence of event and requires just one line:

a.       Serial
b.      Parallel
c.       Both a & b
d.      None of these

79.  Modes of transfer b/w computer and I/O device are:
a.       Programmed I/O
b.      Interrupt-initiated I/O
c.       DMA
d.      Dedicated processor such as IOP and DCP
e.       All of these
80.  ______operations are the results of I/O operations that are written in the computer program:

a.       Programmed I/O
b.      DMA
c.       Handshaking
d.      Strobe

81.  _______is a dedicated processor that combines interface unit and DMA as one unit:
a.       Input-Output Processor
b.      Only input processor
c.       Only output processor
d.      None of these
82.  ______is a special purpose dedicated  processor that is designed specially designed for data transfer in network:
a.       Data Processor
b.      Data Communication Processor
c.       DMA Processor
d.      Interrupt Processor
83.  ______processor has to check continuously till device becomes ready for transferring the data:

a.       Interrupt-initiated I/O
b.      DMA
c.       IOP
d.      DCP

84.  Interrupt-driven I/O data transfer technique is based on______ concept:

a.       On demand processing
b.      Off demand processing
c.       Both a & b
d.      None of these

85.  Which technique helps processor to run a program concurrently with I/O operations:

a.       Interrupt driven I/O
b.      DMA
c.       IOP
d.      DCP

86.  3 types of exceptions are:

a.       Interrupts
b.      Traps
c.       System calls
d.      All of these

87.  Which exception is also called software interrupt:

a.       Interrupt
b.      System calls
c.       Traps
d.      All of these

88.     User programs interact with I/O devices through:

a.       Operating system
b.      Hardware
c.       Cpu
d.      Microprocessor

89.  Which table handle store address of interrupt handling subroutine:

a.       Interrupt vector table
b.      Vector table
c.       Symbol link table
d.      None of these

90.  Which technique is used that identifies the highest priority resource by means of software:

a.       Daisy chaining
b.      Polling
c.       Priority
d.      Chaining

91.  ________interrupt establishes a priority  over the various sources to determine which request should be entertained first:

a.       Priority interrupt
b.      Polling
c.       Daisy chaining
d.      None of these

92.  _____method is used to establish priority by serially connecting all devices that request an interrupt:

a.       Polling
b.      Daisy chaining
c.       Priority
d.      None of these

93.  In daisy chaining device 0 will pass signal only if it has:

a.       Interrupt request
b.      No interrupt request
c.       Both a & b
d.      None of these

94.   VAD stands for:

a.       Vector address
b.      Symbol address
c.       Link address
d.      None of these

95.  _______interrupt method uses a register whose bits are set separately by interrupt signal for each device:
a.       Parallel priority interrupt
b.      Serial priority interrupt
c.       Both a & b
d.      None of these
96.  ______register is used whose purpose is to control status of each interrupt request in parallel priority interrupt:

a.       Mass
b.      Mark
c.       Make
d.      Mask

97.  The ANDed output of bits of interrupt register and mask register are set as input of:

a.       Priority decoder
b.      Priority encoder
c.       Priority decoder
d.      Multiplexer

98.  Which 2 output bits of priority encoder are the part of vector address for each interrupt source in parallel priority interrupt:

a.       A0 and A1
b.      A0 and A2
c.       A0 and A3
d.      A1 and A2
99.  What is the purpose

100.           of A0 and A1 output bits of priority encoder in parallel priority:
a.       Tell data bus which device is to entertained and stored in VAD
b.      Tell subroutine which device is to entertained and stored in VAD
c.       Tell subroutine which device is to entertained and stored in SAD
d.      Tell program which device is to entertained and stored in VAD
101.           When CPU invokes a subroutine it performs following functions:
a.       Pushes updated PC content(return address) on stack
b.      Loads PC with starting address of subroutine
c.       Loads PC with starting address of ALU
d.      Both a & b
102.          DMAC stands for:
a.       Direct memory access controller
b.      Direct memory accumulator controller
c.       Direct memory access content
d.      Direct main access controller
103.          IOP stands for:
a.       Input output processor
104.          DCP stands for:
a.       Data communication processor
105.          Which may be classified as a processor with the direct memory access capability that communicates with I/O devices:

a.       DCP
b.      IOP
c.       Both
d.      None

106.           The processor that communicates with remote terminals like telephone or any other serial communication media in serial fashion is called ______:

a.       DCP
b.      IOP
c.       Both
d.      None

107.          Instruction that are used for reading from memory by an IOP called _______:

a.       Commands
b.      Block diagram
c.       Interrupt
d.      None of these

108.          Data communication with a remote device a special data communication is used_______:

a.       Multiprocessor
b.      Serial communication
c.       DCP
d.      IOP

109.          CRC stands for:
a.       Cyclic redundancy check
110.          Which is used for synchronous data, PID is process ID, followed by message, CRC code and EOP indicating end of block:

a.       DCP
b.      CRC
c.       IOP
d.      SYNC

111.          Which is commonly used in high –speed devices to realize full efficiency of communication link:
a.       Transmission
b.      Synchronous communication
c.       Multiprocessor
d.      All of these
112.          Multiprocessor use ________ than two CPUs assembled in single system unit:

a.       One or More
b.      Two or More
c.       One or One
d.      Two or Two

113.          Which refers the execution of various software process concurrently:

a.       Multiprocessor
b.      Serial communication
c.       DCP
d.      IOP

114.          Which is used for this and known as high speed buffer exist with almost each process?

a.       Primary
b.      RAM
c.       Cache
d.      None of these

115.          Data and instructions are accessed from local memory and global memory that is used by_____:
a.       Internetworking facilities
b.      Interconnection facilities
c.       Both a & b
d.      None of these 
116.          Multiprocessor uses large caches but limited process that shares________
a.       Memory bus
b.      Single memory bus
c.       Double memory bus
d.      None of these
117.          Distributed are shares also referred to as tightly coupled and loosely coupled multiprocessor respectively and hence called __________
a.       Coupled multiprocessor
b.      Shared multiprocessor
c.       Distributed multiprocessor
d.      None of these
118.          Which consist if a numbers of processor can be accessed among various shared memory modules?
a.       Coupled memory multiprocessor
b.      Shared memory multiprocessor
c.       Distributed memory multiprocessor
d.      None of these
119.          Which keeps a number of processors in which virtual storage space is assigned for redundant execution:
a.       Coupled memory multiprocessor
b.      Shared memory multiprocessor
c.       Distributed memory multiprocessor
d.      None of these
120.          The memory capacity in system is considered because the connecting processors are used______:

a.       Network
b.      Internet
c.       Intranet
d.      None of these

121.          Intercrosses arbitration system for multiprocessor shares a _________:

a.       Primary bus
b.      Common bus
c.       Domain bus
d.      All of these

122.          Which is used to decentralize the decision to avail greater flexibility to the system that makes processor or microprocessor in a very short:

a.       Arbitration
b.      Centralized
c.       Both a & b
d.      None of these

123.          Which is signal tells that an arbitration of the access bus is possible during interprocessing:

a.       DBA
b.      BAP
c.       BNA
d.      None of these

124.          Which signal bus request :

a.       BAP
b.      BNA
c.       BAL
d.      DBA

125.           Which signal on the bus indicates that request from process arbitration is to be processed:

a.       BAL
b.      BREQ
c.       BM4
d.      DBA

126.          Which signal is exchange information by bus:

a.       BECH
b.      BM4
c.       BAL
d.      All of these

127.          Which signal on bus applies +1 to the priority of resolution circuits of the arbitration designate a new arbitration:

a.       BM4
b.      BAL
c.       BNA
d.      DBA

128.          Which signal create 3 lines of bus in which signals from the encoded number of processors:

a.       BM1 to BM3
b.      BAL
c.       Both
d.      None of these

129.          Which signal request the validation signal make active if its logic level is 0 and validate signals from BM1 to BM3:

a.       BAL
b.      BM4
c.       BNA
d.      All of these

130.          Which signal represents synchronization signal decided by interprocess arbitration with a certain delay or signal DMA:

a.       BAL
b.      BNA
c.       Both
d.      None of these

131.           In which condition only one process holds a resource at a given time:

a.       Mutual exclusion
b.       Hold and wait
c.       Both
d.      None of these

132.          In which condition one process holds the allocated resources and other waits for it:

a.       No preemption
b.      Hold and wait
c.       Mutual exclusion
d.      All of these

133.          In which condition resource is not removed from a process holding:

a.       Synchronization problem
b.      No preemption
c.       Hold and wait
d.      None of these

134.          In which condition busy waiting, programmer error, deadlock or circular wait occurs in interprocessing:

a.       Synchronization problem
b.      No preemption
c.       Hold and wait
d.      None of these

135.          Mechanism can be referred to as adding a new facility to the system hence known as _______:

a.       Process
b.      Arbitration
c.       Both a & b
d.      None of these

136.          Which is a mechanism used by the OS to ensure a systematic sharing of resources amongst concurrent resources:

a.       Process synchronous
b.      Process system
c.       Process synchronization
d.      All of these

137.          _________ is basically sequence of instructions with a clear indication of beginning and end for updating shared variables

a.       Critical section
b.      Entry section
c.       Remainder section
d.      All of these

138.          Which provides a direct hardware support to mutual exclusion

a.       Test-and-set(TS)
b.      Swap instruction
c.       Wait instruction
d.      Signal instruction

139.          A process waiting to enter its critical section may  have to wait for unduly_______:
a.       Short time or may have to wait forever
b.      Long  time or may have to wait forever
c.       Short time or may have to wait for long time
d.      Long time or may have to wait for short time
140.          Which is a modified version of the TS instruction which is designed to remove busy- waiting:

a.        Swap instruction
b.      Wait instruction
c.       Signal instruction
d.      Both b & c

141.          PCB stands for:
a.       Process control block
142.          ____ gets activated whenever the process encounters a busy condition code:

a.       Wait instruction
b.      Signal instruction
c.       Both a & b
d.      None of these

143.          _____ are new and mutually exclusive operation:

a.       Wait instruction
b.      Signal instruction
c.       Both a & b
d.      None of these

144.          _______ gets activated whenever a process leaves the critical region and the flag is set to false:

a.       Wait instruction
b.      Signal instruction
c.       Both a & b
d.      None of these

145.          Which represent an abstraction of many important ideas in mutual exclusion:

a.       Process synchronous
b.      Process system
c.       Semaphores
d.      All of these

146.          A semaphore is a ______ integer variable upon which two atomic operations wait and signal are defined:
a.       Negative integer
b.      Non- Negative integer
c.       Positive integer
d.      None of these
147.          Which operation is executed as soon as a process exits from a critical section:

a.       Wait
b.      Signal
c.       Both a & b
d.      None of these

148.          CCR stands for:
a.       Conditional critical region
149.          ________ is a control structure in a high-level programming language:

a.       CPU
b.      ALU
c.       DDR
d.      CCR

150.          The exclusion between processes is ensured by a third semaphore called______:

a.       Mutex
b.      Mutual
c.       Memory
d.      All of these

151.          ______ semaphore provides mutual exclusion  for accesses to the buffer pool and is initialized to the value:

a.       Mutex
b.      Mutual
c.       Memory
d.      All of these

152.          Which processes access and manipulate the shared data concurrently:

a.       Micro processes
b.      Several processes
c.       Both
d.      None of these

153.          Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables:

a.       Racing section
b.      Critical section
c.       Both
d.      None of these

154.          In which section only one process is allowed to access the shared variable and all other have to wait:

a.       Critical section
b.      Racing section
c.       Entry section
d.      Remainder section

155.          Which are the problem of critical section:

a.       Mutual exclusion
b.      Progress
c.       Bounded wait
d.      All of these

156.          Which section refer to the code segment of a process that is executed when the process intends to enter its critical section:

a.       Critical section
b.      Entry section
c.       Reminder section
d.      None of these

157.          Which section refer to the code segment where a shared resource is accessed by the process:

a.       Reminder section
b.      Entry section
c.       Both
d.      None of these

158.          Which section is the remaining part of a process’s code:

a.       Racing section
b.      Critical section
c.       Entry section
d.      Reminder section

159.          How many conditions for controlling access to critical section:

a.       2
b.      4
c.       3
d.      5

160.          Which instruction provides a direct hardware support to mutual exclusion:

a.       SP instruction
b.      TS instruction
c.       Both
d.      None of these

161.           Which instruction also improves the efficiency of the system:

a.       Swap instruction
b.      TS instruction
c.       Both
d.      None of these

162.            Which instruction allows only one concurrent process to enter the critical section:

a.       RP instruction
b.      SP instruction
c.       TS instruction
d.      None of these

163.          Which section problem can be solved simply in a uniprocessor environment if the we are able to prevent the occurrence of interrupt during the modification of a shared variable:

a.       Entry section
b.      Critical section
c.       Non-critical section
d.      None of these

e.        
164.          The problem of readers and writers was first formulated by ________:

a.       P.J. Courtois
b.      F.Heymans
c.       D.L. Parnas
d.      All of these

165.          Which is a situation in which some process wait for each other’s actions indefinitely:

a.       Operating system
b.      Deadlock
c.       Mutex
d.      None of these

166.          _________system handles only deadlocks caused by sharing of resources in the system:

a.       Operating system
b.      Deadlock
c.       Mutex
d.      None of these

167.          A deadlocks occurs when the how many conditions are met:

a.       1
b.      2
c.       3
d.      4

168.          Which are the characteristics of deadlocks:

a.       Mutual exclusion
b.      Hold and wait
c.       No pre-emption
d.      Circular wait
e.       All of these

169.          RAG stands for:
a.       Resource allocation graph
170.          How many events concerning RAG can occur in a system:

a.       1
b.      2
c.       3
d.      4

171.          Which are the events concerning RAG can occur in a system:

a.       Request for a resource
b.      Allocation of a resource
c.       Release of resource
d.      All of these

172.          How many methods for handling deadlocks:

a.       1
b.      2
c.       3
d.      4

173.          Which are the method for handling deadlocks:

a.       Deadlock prevention
b.      Deadlock avoidance
c.       Deadlock detection
d.      All of these

174.          How many condition that should be met in order to produce a deadlock:

a.       2
b.      4
c.       6
d.      8

175.          Which are the condition that should be met in order to produce a deadlock:

a.       Mutual exclusion
b.      Hold and Wait
c.       No preemption
d.      Circular wait
e.       All of these

176.          In protocol each process can make a request only in an ________:

a.       Increasing order
b.      Decreasing order
c.       Both a & b
d.      None of these

177.          In protocol above mentioned ________protocol are used then the circular wait-condition can not hold:

a.       1
b.      2
c.       3
d.      4

178.          Which state refers to a state that is not safe not necessarily a deadlocked state:

a.       Safe state
b.      Unsafe state
c.       Both a & b
d.      None of these

179.          ________ a direct arrow is drawn from the process to the resource rectangle to represent each pending resource request:

a.       TS
b.      SP
c.       CCR
d.      RAG

180.          The attributes of a file are:
a.       Name
b.      Identifier
c.       Types
d.      Location
e.       Size
f.        Protection
g.       Time, date and user identification
h.       All of these
181.          The various file operation are:
a.       Crating a file
b.      Writing a file
c.       Reading a file
d.      Repositioning within a file
e.       Deleting a file truncating a file
f.        All of these
182.          Which operations are to be performed on a directory are:

a.       Search for a file
b.      Create a file
c.       Delete a file
d.      List a directory
e.       Rename a file
f.        Traverse the file system
g.       All of these

183.          Which memory is assembled between main memory and CPU:

a.       Primary memory
b.      Cache memory
c.       Both a & b
d.      None of these

184.          Which is considered as semi-conductor memory , which is made up of static RAM:

a.        Primary memory
b.      Cache memory
c.       Both a & b
d.      None of these

185.          Which is one of the important I/O devices  and is most commonly used  as permanent storage device in any processor:

a.       Soft disk
b.      Hard disk
c.       Both a & b
d.      None of these

186.          ______ can read any printed character by comparing the pattern that is stored in the computer:

a.       SP
b.      CCR
c.       RAG
d.      OCR

187.          Which system is a typical example of the readers and writers problem:
a.       Airline reservation system
b.      Airport reservation system
c.       Both
d.      None of these
188.          Which lock can arise when two processes wait for phone calls from one another:

a.       Spine lock
b.      Dead lock
c.       Both
d.      None of these

189.          Which lock is more serious than indefinite postponement or starvation because it affect more than one job:

a.       Deadlock
b.      Spinelock
c.       Both
d.      None of these


3 comments:

  1. thanks a lot for this
    It will be to better if u could explain why the choosen answer is correct.

    ReplyDelete
  2. interrupt driven I/O data transfer technique is based on ------ concept.

    ReplyDelete
  3. interrupt driven I/O data transfer technique is based on ------ concept.

    ReplyDelete