1) Who
is the brain of computer:
a.
ALU
b.
CPU
c.
MU
d.
None of these
2) Which
technology using the microprocessor is fabricated on a single chip:
a.
POS
b.
MOS
c.
ALU
d.
ABM
3) MOS
stands for:
a.
Metal oxide
semiconductor
b.
Memory oxide semiconductor
c.
Metal oxide select
d.
None of these
4) In
which form CPU provide output:
a.
Computer signals
b.
Digital
signals
c.
Metal signals
d.
None of these
5) How
many types of microprocessor comprises:
a.
3
b.
6
c.
9
d.
4
6) Which
is the microprocessor comprises:
a.
Register section
b.
One or more ALU
c.
Control unit
d.
All of these
7) The
register section is related to______ of the computer:
a.
Processing
b.
ALU
c.
Main memory
d.
None of these
8) What is the store by register:
a.
data
b.
operands
c.
memory
d.
None of these
9) How many types of classification of processor
based on register section:
a.
1
b.
2
c.
3
d.
4
10) In
Microprocessor one of the operands holds a special register called:
a.
Calculator
b.
Dedicated
c.
Accumulator
d.
None of these
11) Accumulator
based microprocessor example are:
a.
Intel 8085
b.
Motorola 6809
c.
A and B
d.
None of these
12) A set of
register which contain are:
a.
data
b.
memory addresses
c.
result
d.
all of these
13) How many
types are primarily register:
a.
1
b.
2
c.
3
d.
4
14) There are
primarily two types of register:
a.
general purpose register
b.
dedicated register
c.
A and B
d.
none of these
15) Which
register is a temporary storage location:
a.
general purpose register
b.
dedicated register
c.
A and B
d.
none of these
16) How many
parts of dedicated register:
a.
2
b.
4
c.
5
d.
6
17) Name of
typical dedicated register is:
a.
PC
b.
IR
c.
SP
d.
All of these
18) PC stands
for:
a.
Program
counter
b.
Points counter
c.
Paragraph counter
d.
Paint counter
19) IR stands
for:
a.
Intel register
b.
In counter register
c.
Index register
d.
Instruction
register
20) SP stands
for:
a.
Status pointer
b.
Stack
pointer
c.
a and b
d.
None of these
21) The act of
acquiring an instruction is referred as the____ the instruction:
a.
Fetching
b.
Fetch cycle
c.
Both a and b
d.
None of these
22) How many
bit of instruction on our simple computer consist of one____:
a.
2-bit
b.
6-bit
c.
12-bit
d.
None of these
23) How many
parts of single address computer instruction :
a.
1
b.
2
c.
3
d.
4
24) Single
address computer instruction has two parts:
a.
The operation code
b.
The operand
c.
A and B
d.
None of these
25) LA stands
for:
a.
Load
accumulator
b.
Least accumulator
c.
Last accumulator
d.
None of these
26) ED stands
for:
a.
Enable MRD
b.
Enable MDR
c.
Both a and b
d.
None of these
27) LM stands
for:
a.
Least MAR
b.
Load MAR
c.
Least MRA
d.
Load MRA
28) Causing a
flag to became 0 is called:
a.
Clearing a
flag
b.
Case a flag
c.
Both a and b
d.
None of these
29) Which are
the flags of status register:
a.
Over flow flag
b.
Carry flag
c.
Half carry flag
d.
Zero flag
e.
Interrupt flag
f.
Negative flag
g.
All of these
30) The carry
is operand by:
a.
C
31) The sign is
operand by:
a.
S
32) The zero is
operand by:
a.
Z
33) The
overflow is operand by:
a.
O
34) _____ is
the condition:
a.
CD
b.
IR
c.
Both a and b
d.
None of these
35) ____ causes
the address of the next microprocessor to be obtained from the memory:
a.
CRJA
b.
ROM
c.
MAP
d.
HLT
36) _________
Stores the instruction currently being executed:
a.
Instruction
register
b.
Current register
c.
Both a and b
d.
None of these
37) In which
register instruction is decoded prepared and ultimately executed:
a.
Instruction register
b.
Current register
c.
Both a and b
d.
None of these
38) The status
register is also called the____:
a.
Condition code register
b.
Flag register
c.
A and B
d.
None of these
39) BCD stands
for:
a.
Binary coded
decimal
b.
Binary coded decoded
c.
Both a & b
d.
none of these
40) Which is
used to store critical pieces of data during subroutines and interrupts:
a.
Stack
b.
Queue
c.
Accumulator
d.
Data register
41) The area of
memory with addresses near zero are called:
a.
High memory
b.
Mid memory
c.
Memory
d.
Low memory
42) The point
where control returns after a subprogram is completed is known as the :
a.
Return
address
b.
Main Address
c.
Program Address
d.
Current Address
43) The
subprogram finish the return instruction recovers the return address from the:
a.
Queue
b.
Stack
c.
Program counter
d.
Pointer
44) The
processor uses the stack to keep track of where the items are stored on it this
by using the:
a.
Stack
pointer register
b.
Queue pointer register
c.
Both a & b
d.
None of these
45) Which point
to the ___ of the stack:
a.
TOP
b.
START
c.
MID
d.
None of these
46) Stack words
on:
a.
LILO
b.
LIFO
c.
FIFO
d.
None of these
47) Which is
the basic stack operation:
a.
PUSH
b.
POP
c.
BOTH A and B
d.
None of these
48) SP stand
for:
a.
Stack
pointer
b.
Stack pop
c.
Stack push
d.
None of these
49) How many
bit stored by status register:
a.
1 bit
b.
4 bit
c.
6 bit
d.
8 bit
50) Which is
the important part of a combinational logic block:
a.
Index register
b.
Barrel
shifter
c.
Both a & b
d.
None of these
51) The
structure of the stack is _______ type structure:
a.
First in
last out
b.
Last in last out
c.
Both a & b
d.
None of these
52) The data in
the stack is called:
a.
Pushing data
b.
Pushed
c.
Pulling
d.
None of these
53) The CU is
designed by using which techniques:
a.
HARDWIRED CONTROLS
b.
MICROPROGRAMING
c.
NANOPROGRAMING
d.
ALL OF THESE
54) The 16 bit
register is separated into groups of 4 bit where each groups is called:
a.
BCD
b.
Nibble
c.
Half byte
d.
None of these
55) A nibble
can be represented in the from of:
a.
Octal digit
b.
Decimal
c.
Hexadecimal
d.
None of these
56) The left
side of any binary number is called:
a.
Least significant digit
b.
Most
significant digit
c.
Medium significant digit
d.
low significant digit
57) MSD stands
for:
a.
Least significant digit
b.
Most significant
digit
c.
Medium significant digit
d.
low significant digit
58) _____ a
subsystem that transfer data between computer components inside a computer or
between computer:
a.
Chip
b.
Register
c.
Processor
d.
Bus
59) Which is
called superhighway:
a.
Processor
b.
Multiplexer
c.
Backbone bus
d.
None of these
60) The
external system bus architecture is created using from ______ architecture:
a.
Pascal
b.
Dennis Ritchie
c.
Charles Babbage
d.
Von Neumann
61) The network
of wires or electronic path ways on mother board back side:
a.
PCB
b.
BUS
c.
BOTH A and B
d.
None of these
62) Which Bus
connects CPU & level 2 cache:
a.
Rear side bus
b.
Front side
bus
c.
Memory side bus
d.
None of these
63) Which bus
carry addresses:
a.
System bus
b.
Address bus
c.
Control bus
d.
Data bus
64) A 16 bit
address bus can generate___ addresses:
a.
32767
b.
25652
c.
65536
d.
none of these
65) The processor
80386/80486 and the Pentium processor uses _____ bits address bus:
a.
16
b.
32
c.
36
d.
64
66) CPU can read
& write data by using :
a.
Control bus
b.
Data bus
c.
Address bus
d.
None of these
67) Which bus
transfer singles from the CPU to external device and others that carry singles
from external device to the CPU:
a.
Control bus
b.
Data bus
c.
Address bus
d.
None of these
68) Which is
not the control bus signal:
a.
READ
b.
WRITE
c.
RESET
d.
None of these
69) When memory
read or I/O read are active data is to the processor :
a.
Input
b.
Output
c.
Processor
d.
None of these
70) When memory
write or I/O read are active data is from the processor:
a.
Input
b.
Output
c.
Processor
d.
None of these
71) Using 12
binary digits how many unique house addresses would be possible:
a.
28=256
b.
212=4096
c.
216=65536
d.
None of these
72) PROM stands
for:
a.
Programmable
read-only memory
73) EPROM
stands for:
a.
Erasable
Programmable read-only memory
74) Each memory
location has:
a.
Address
b.
Contents
c.
Both A and B
d.
None of these
75) Which is
the type of microcomputer memory:
a.
Processor memory
b.
Primary memory
c.
Secondary memory
d.
All of these
76) Secondary memory
can store____:
a.
Program store code
b.
Compiler
c.
Operating system
d.
All of these
77) Secondary
memory is also called____:
a.
Auxiliary
b.
Backup store
c.
Both A and B
d.
None of these
78) Customized
ROMS are called:
a.
Mask ROM
b.
Flash ROM
c.
EPROM
d.
None of these
79) The ram
which is created using bipolar transistors is called:
a.
Dynamic RAM
b.
Static RAM
c.
Permanent RAM
d.
DDR RAM
80) Which type
of RAM needs regular referred:
a.
Dynamic RAM
b.
Static RAM
c.
Permanent RAM
d.
SD RAM
81) Which RAM
is created using MOS transistors:
a.
Dynamic RAM
b.
Static RAM
c.
Permanent RAM
d.
SD RAM
82) Which latch
is mostly used creating memory register:
a.
SR-Latch
b.
JK-Latch
c.
D-Latch
d.
T-Latch
83) Which
statement is false about WR signal:
a.
WR signal controls the input buffer
b.
The bar over WR means that this is an active low signal
c.
The bar over
WR means that this is an active high
signal
d.
If WR is 0 then the input data reaches the latch input
84) Which
technique is used for main memory array design:
a.
Linear decoding
b.
Fully decoding
c.
Both A and B
d.
None of these
85) CS stands
for:
a.
Cable select
b.
Chip select
c.
Control select
d.
Cable system
86) WE stands
for:
a.
Write enable
b.
Wrote enable
c.
Write envy
d.
None of these
87) When CS
_____ the chip is not selected at all hence D7 to D0 are driven to high
impedance state:
a.
High
b.
Low
c.
Medium
d.
Stand by
88) The
capacity of this chip is 1KB they are organized in the form of 1024 words with
8 bit word The what is the site of
address bus:
a.
8 bit
b.
10 bit
c.
12 bit
d.
16 bit
89) Which
storage technique dose not decoding circuit:
a.
Linear
decoding
b.
Fully decoding
c.
Partially
d.
None of these
90) In linear decoding address bus of 16-bit wide
can connect only ____ of RAM.
a.
16 KB
b.
6KB
c.
12KB
d.
64KB
91) Which
statement is wrong according to linear decoding :
a.
Address map is not contiguous.
b.
Confects occur if two of the select lines become active
at the same time
c.
If all unused address lines are not used as chip
selectors then these unused lines become don’t cares
d.
None of
these
92) The problem
of bus confect and sparse address distribution are eliminated by the use of
______ address technique:
a.
Fully
decoding
b.
Half decoding
c.
Both a & b
d.
None of these
93) A
microprocessor retries instructions from :
a.
Control memory
b.
Cache memory
c.
Main memory
d.
Virtual memory
94) Which register is used to communicate with memory:
a.
MAR
b.
MDR
c.
Both A and B
d.
None of these
95) SAM stands
for:
a.
Simple
architecture machine
b.
Solved
architecture machine
c.
Both a & b
d.
None of these
96) MAR stands
for:
a.
Memory
address register
b.
Memory address recode
c.
Micro address register
d.
None of these
97) MDR stands
for:
a.
Memory data
register
b.
Memory data recode
c.
Micro data register
d.
None of these
98) VAM stands
for:
a.
Valid memory
address
b.
Virtual memory address
c.
Variable memory address
d.
None of these
99) Which microprocessor to read an item from
memory:
a.
VAM
b.
SAM
c.
MOC
d.
None of these
100)
Which bus plays a crucial role in I/O:
a.
System bus
b.
Control bus
c.
Address bus
d.
Both A and B
101)
Which register is connected to the memory by way of the
address bus:
a.
MAR
b.
MDR
c.
SAM
d.
None of these
102)
How many bit of MAR register:
a.
8-bit
b.
16-bit
c.
32-bit
d.
64-bit
103)
MOC stands for:
a.
Memory operation complex
b.
Micro operation complex
c.
Memory
operation complete
d.
None of these
104)
Which are the READ operation can in simple steps:
a.
Address
b.
Data
c.
Control
d.
All of these
105)
The upper red arrow show that CPU sends out the control
signals____ and _____ indicate the data is read from the memory:
a.
Memory request
b.
Read
c.
Both A and B
d.
None of these
106)
The information
is transferred from the_____ and ____ specified register:
a.
MDR
b.
CPU
c.
Both A and B
d.
None of these
107)
The information on the data bus is transferred to the
______register:
a.
MOC
b.
MDR
c.
VAM
d.
CPU
108)
The lower red curvy arrow show that CPU places the
address extracted from the memory location on the_____:
a.
Address bus
b.
System bus
c.
Control bus
d.
Data bus
109)
DMA stands for:
a.
Direct
memory access
b.
Direct memory allocation
c.
Data memory access
d.
Data memory allocation
110)
DMA stands for:
a.
Dynamic memory access
b.
Data memory access
c.
Direct memory access
d.
Both B and C
111)
CRT stands for:
a.
Cathode ray
tube
b.
Compared ray tube
c.
Command ray tube
d.
None of these
112)
The CPU sends out a ____ signal to indicate that valid
data is available on the data bus:
a.
Read
b.
Write
c.
Both A and B
d.
None of these
113)
The ____ place the data from a register onto the data
bus:
a.
CPU
b.
ALU
c.
Both A and B
d.
None of these
114)
The CPU removes
the ___ signal to complete the memory
write operation:
a.
Read
b.
Write
c.
Both A and B
d.
None of these
115)
The value memvar must
be transferred to the ___:
a.
Computer
b.
CPU
c.
Both A and B
d.
None of these
116)
The microcomputer system by using the ____device
interface:
a.
Input
b.
Output
c.
Both A and B
d.
None of these
117)
How bit microprocessor inexpensive a separate interface
is provided with I/O device:
a.
2 bit
b.
4 bit
c.
8 bit
d.
32 bit
118)
How many ways of transferring data between the
microprocessor and a physical I/O device:
a.
2
b.
3
c.
4
d.
5
119)
The standard I/O is also called:
a.
Isolated I/O
b.
Parallel I/O
c.
both a and b
d.
none of these
120)
standard I/O uses which control pin on the micro
processor:
a.
IO/M
121)
A___ on this pin indicates a memory operation:
a.
Low
b.
High
c.
Medium
d.
None of these
122)
The external device is connected to a pin called the
______ pin on the processor chip.
a.
Interrupt
b.
Transfer
c.
Both
d.
None of these
123)
The DMA controllers are special hardware embedded into
the chip in modern integrate processor that ____and_____ to the system;
a.
Data transfer
b.
arbitrate access
c.
Both A and B
d.
None of these
124)
The CPU completes yields control of the bus to the DMA
controller via:
a.
DMA
acknowledge signal
b.
DMA integrated signal
c.
DMA implicitly signal
d.
None of these
125)
The mode of DMA are:
a.
Single transfer
b.
Block transfer
c.
Burst –block transfer
d.
Repeated single transfer
e.
Repeated–block transfer
f.
Repeated Burst –block transfer
g.
All of these
This comment has been removed by the author.
ReplyDeleteThis comment has been removed by the author.
ReplyDelete