1. _____
is a command given to a computer to perform a specified operation on some given
data:
a.
An
instruction
b. Command
c. Code
d. None
of these
2. An
instruction is guided by_____ to perform work according:
a. PC
b. ALU
c. Both
a and b
d.
CPU
3. Two
important fields of an instruction are:
a. Opcode
b. Operand
c. Only
a
d.
Both a &
b
4. Each
operation has its _____ opcode:
a.
Unique
b. Two
c. Three
d. Four
5. which
are of these examples of Intel 8086 opcodes:
a. MOV
b. ADD
c. SUB
d.
All of these
6. _______specify
where to get the source and destination operands for the operation specified by
the _______:
a.
Operand
fields and opcode
b. Opcode
and operand
c. Source
and destination
d. Cpu
and memory
7. The
source/destination of operands can be the_______ or one of the general-purpose
register:
a.
Memory
b. One
c. both
d. None
of these
8. The
complete set of op-codes for a particular microprocessor defines the______ set
for that processor:
a. Code
b. Function
c. Module
d.
Instruction
9. Which
is the method by which instructions are selected for execution:
a. Instruction
selection
b. Selection
control
c.
Instruction
sequencing
d. All
of these
10. The
simplest method of controlling sequence of instruction execution is to have
each instruction explicitly specify:
a.
The address
of next instruction to be run
b. Address
of previous instruction
c. Both
a & b
d. None
of these
11. As the
instruction length increases ________ of instruction addresses in all the
instruction is_______:
a. Implicit
inclusion
b. Implicit
and disadvantageous
c.
Explicit and
disadvantageous
d. Explicit
and disadvantageous
12. ______is the sequence of operations performed
by CPU in processing an instruction:
a. Execute
cycle
b. Fetch
cycle
c. Decode
d.
Instruction
cycle
13. The time
required to complete one instruction is called:
a. Fetch
time
b.
Execution
time
c. Control
time
d. All
of these
14. _____is the
step during which a new instruction is read from the memory:
a. Decode
b.
Fetch
c. Execute
d. None
of these
15. ________is
the step during which the operations specified by the instruction are executed:
a.
Execute
b. Decode
c. Both
a& b
d. None
of these
16. Decode is
the step during which instruction is______:
a. Initialized
b. Incremented
c.
Decoded
d. Both
b & c
17. The
instruction fetch operation is initiated by loading the contents of program counter into the______ and sends_____
request to memory:
a. Memory
register and read
b. Memory
register and write
c. Data
register and read
d.
Address
register and read
18. The
contents of the program counter is the _______ of the instruction to be run:
a. Data
b.
Address
c. Counter
d. None
of these
19. The
instruction read from memory is then placed in the_______ and contents of program counter is______ so that it contains
the address of_______ instruction in the program:
a. Program
counter, incremented and next
b. Instruction
register, incremented and previous
c.
Instruction
register, incremented and next
d. Address
register, decremented and next
20. Execution
of instruction specified by instruction to perform:
a.
Operation
b. Operands
c. Both
a & b
d. None
of these
21. _______ is
a symbolic representation of discrete elements of information:
a. Data
b.
Code
c. Address
d. Control
22. Group of
binary bits(0&1) is known as:
a.
Binary code
b. Digit
code
c. Symbolic
representation
d. None
of these
23. A group of
4 binary bits is called:
a.
Nibble
b. Byte
c. Decimal
d. Digit
24. BCD uses
binary number system to specify decimal numbers:
a. 1-10
b. 1-9
c.
0-9
d. 0-10
25. The ______
are assigned according to the position occupied by digits:
a. Volume
b.
Weight
c. Mass
d. All
of these
26. what is the
BCD for a decimal number 559:
a.
[0101 0101
1001]BCD
b. [0101
0001 1010]
c. [0101
1001 1001]
d. [1001
1010 0101]
27. ________are
the codes that represent alphabetic characters, punctuation marks and other
special characters:
a.
Alphanumeric
codes
b. ASCII
codes
c. EBCDIC
codes
d. All
of these
28. Abbreviation ASCII stands for:
a.
American
standard code for information interchange
b. Abbreviation
standard code for information interchange
c. Both
d. None
of these
29. How many
bit of ASCII code:
a. 6
b.
7
c. 5
d. 8
30. Which code
used in transferring coded information from keyboards and to computer display
and printers:
a.
ASCII
b. EBCDIC
c. Both
d. None
of these
31. Which code used to represent numbers, letters,
punctuation marks as well as control characters:
a.
ASCII
b. EBCDIC
c. Both
d. None
of these
32. abbreviation
EBCDIC stand for:
a.
Extended
binary coded decimal interchange code
b. External
binary coded decimal interchange code
c. Extra
binary coded decimal interchange code
d. None
of these
33. How
many bit of EBCDIC code:
a. 7
b.
8
c. 5
d. 9
34. Which code
the decimal digits are represented by the 8421 BCD code preceded by 1111:
a. ASCII
b.
EBCDIC
c. Both
d. None
of these
35. _________ has the property that corrupting or garbling
a code word will likely produce a bit string that is not a code word:
a. Error
deleting codes
b.
Error
detecting codes
c. Error
string codes
d. None
of these
36. Which is
method used most simple and commonly:
a.
Parity check
method
b. Error
detecting method
c. Both
d. None
of these
37. Which is
the method of parity:
a. Even
parity method
b. Odd
parity method
c.
Both
d. None
of these
38. The ability
of a code to detect single errors can be stated in term of the _________:
a.
Concept of
distance
b. Even
parity
c. Odd
parity
d. None
of these
39. The first n
bit of a code word called __________ may be any of the 2n n- bit
string minimum error bit:
a.
Information
bits
b. String
bits
c. Error
bits
d. All
of these
40. A code in
which the total number of 1s in a valid (n+1) bit code word is even, this is
called an __________:
a.
Even parity
code
b. Odd
parity code
c. Both
d. None
of these
41. A code in
which the total number of 1s in a valid (n+1)bit code word is odd and this code
is called an__________:
a. Error
detecting code
b. Even
parity code
c.
Odd parity
code
d. None
of these
42. a code is
simply a subset of the vertices of the _____:
a. n
bit
b.
n cube
c. n
single
d. n
double
43. Which
method is used to detect double errors and pinpoint erroneous bits:
a. Even
parity method
b. Odd
parity method
c.
Check sum
method
d. All
of these
44. A code that
is used to correct error is called an _________:
a. Error
detecting code
b.
Error
correcting code
c. Both
d. None
of these
45. A received ___________with
a bit error will be closer to the originally transmitted code word than to any
other code word:
a. Code
word
b.
Non code
word
c. Decoding
d. All
of these
46. Which code
word was originally transmitted to produce a received word is called:
a. Non
code word
b. Code
word
c.
Decoding
d. None
of these
47. The
hardware that does this is an ________:
a. Error
detecting decoder
b.
Error
correcting decoder
c. Both
d. None
of these
48. Hamming
codes was developed in __________:
a. 1953
b.
1950
c. 1945
d. 1956
49. ____________
between two code words is defined as the number of bits that must be changed
for one code to another:
a. Hamming
codes
b.
Hamming
distance
c. Both
d. None
of these
50. It is
actually a method for constructing codes with a minimum distance of ____:
a. 2
b. 4
c.
3
d. 5
51. The bit
position in a ___________ can be numbered from 1 through 2i-1:
a.
Hamming code
word
b. Hamming
distance word
c. Both
d. None
of these
52. Each check bit is grouped with the information
bits as specified by a____________:
a. Parity
check code
b.
Parity check
matrix
c. Parity
check bit
d. All
of these
53. The pattern of groups that have odd parity
called the _________must match one of the of columns in the parity check
matrix:
a.
Syndrome
b. Dynodes
c. Both
d. None
of these
54. Which are
designed to interpret a specified number of instruction code:
a. Programmer
b.
Processors
c. Instruction
d. Opcode
55. Which code
is a string of binary digits:
a. Op
code
b.
Instruction
code
c. Parity
code
d. Operand
code
56. The list of
specific instruction supported by the CPU is termed as its ____________:
a. Instruction
code
b. Parity
set
c.
Instruction
set
d. None
of these
57. __________is
divided into a number of fields and is represented as a sequence of bits:
a.
instruction
b. instruction
set
c. instruction
code
d. parity
code
58. Which unit
is necessary for the execution of instruction:
a. Timing
b. Control
c.
Both
d. None
of these
59. Which unit
provide status , timing and control signal:
a.
Timing and
control unit
b. Memory
unit
c. Chace
unit
d. None
of these
60. Which unit
acts as the brain of the computer which control other peripherals and
interfaces:
a. Memory
unit
b. Cache
unit
c.
Timing and
control unit
d. None
of these
61. It contains
the ____________stack for PC storage during subroutine calls and
input/output interrupt services:
a. Seven-
level hardware
b.
Eight- level
hardware
c. One-
level hardware
d. Three-
level hardware
62. Which unit
works as an interface between the processor and all the memories on chip or
off- chip:
a. Timing
unit
b. Control
unit
c.
Memory
control unit
d. All
of these
63. The maximum
clock frequency is_______:
a. 45
MHZ
b.
50 MHZ
c. 52
MHZ
d. 68
MHZ
64. ________ is
given an instruction in machine language this instruction is fetched from the
memory by the CPU to execute:
a. ALU
b.
CPU
c. MU
d. All
of these
65. Which
cycle refers to the time period during which one instruction is fetched and
executed by the CPU:
a. Fetch
cycle
b.
Instruction
cycle
c. Decode
cycle
d. Execute
cycle
66. How many
stages of instruction cycle:
a. 5
b. 6
c.
4
d. 7
67. Which are stages of instruction cycle:
a. Fetch
b. Decode
c. Execute
d. Derive
effective address of the instruction
e.
All of these
68. Which instruction are 32 bits long , with
extra 16 bits:
a.
Memory
reference instruction
b. Memory
reference format
c. Both
d. None
of these
69. Which is
addressed by sign extending the 16-bit displacement to 32-bit:
a. Memory
address
b.
Effective
memory address
c. Both
a and b
d. None
of these
70. Which are
instruction in which two machine cycle are required:
a. Instruction
cycle
b.
Memory
reference instruction
c. Both
d. None
of these
71. Which
instruction are used in multithreaded parallel processor architecture:
a.
Memory
reference instruction
b. Memory
reference format
c. Both
d. None
of these
72. Which instruction are arranged as per the
protocols of memory reference format of the input file in a simple ASCII
sequence of integers between the range 0 to 99 separated by spaces without
formatted text and symbols:
a.
Memory
reference instruction
b. Memory
reference format
c. Both
d. None
of these
73. ____________
is an external hardware event which causes the CPU to interrupt the current
instruction sequence:
a. Input
interrupt
b. Output
interrupt
c.
Both
d. None
of these
74. ISR stand
for:
a. Interrupt
save routine
b.
Interrupt
service routine
c. Input
stages routine
d. All
of these
75. Which interrupt
services save all the register and flags:
a. Save
interrupt
b.
Input/output
interrupt
c. Service
interrupt
d. All
of these
76. IRET stand
for:
a. Interrupt
enter
b.
Interrupt
return
c. Interrupt
delete
d. None
of these
77. Which are
benefit of input/output interrupt:
a. It
is an external analogy to exceptions
b. The
processor initiates and perform all I/O operation
c. The
data is transferred into the memory through interrupt handler
d.
All of these
78. Which are
the not causes of the interrupt:
a. In
any single device
b. In
processor poll devices
c.
It is an
external analogy to exception
d. None
of these
79. Which are the causes of the interrupt:
a. In
any single device
b. In
processor poll devices
c. In
a device whose ID number is stored on the address bus
d.
All of these
80. Which are
the functioning of I/O interrupt:
a. The
processor organizes all the I/O operation for smooth functioning
b. After
completing the I/O operation the device interrupt the processor
c. Both
d. None
of these
81. _________with
which computers perform is way beyond human capabilities:
a.
Speed
b. Accuracy
c. Storage
d. Versatility
82. _________ of a computer is consistently:
a. Speed
b.
Accuracy
c. Storage
d. Versatility
83. GIGO stand
for:
a.
Garbage-in-garbage-out
b. Garbage-in
garbage-occur
c. Both
d. None
of these
84. How many
basic operations of versatility:
a. 5
b. 6
c.
4
d. 7
85. Which are
the operation of versatility:
a. exchange
of information with the outside world via I/O device
b. Transfer
of data internally with in the central processing unit
c. Performs
of the basic arithmetic operations
d.
All of these
86. ____________ of information in a human brain
and a computer happens differently:
a. Intelligence
b.
Storage
c. Versatility
d. Diligence
87. Which are
the basic operation for converting:
a. Inputting
b. Storing
c. Processing
d. Outputting
e. Controlling
f.
All of these
88. The control
unit and arithmetic logic unit are know as the ___________:
a. Central
program unit
b.
Central
processing unit
c. Central
primary unit
d. None
of these
89. Which unit
is comparable to the central nervous system in the human body:
a. Output
unit
b.
Control unit
c. Input
unit
d. All
of these
90. ___________
of the primary memory of the computer is limited:
a.
Storage
capacity
b. Magnetic
disk
c. Both
d. None
of these
91. Information
is handled in the computer by _________:
a. Electrical
digit
b.
Electrical
component
c. Electronic
bit
d. None
of these
92. 0 and 1 are know as ___________:
a. Byte
b.
Bit
c. Digits
d. Component
93. 0 and 1
abbreviation for:
a.
Binary digit
b. Octal
digit
c. Both
d. None
of these
94. How many bit of nibble group:
a. 5
b.
4
c. 7
d. 8
95. How many
bit of bytes:
a. 3
b. 4
c. 6
d.
8
96. Which is
the most important component of a digit computer that interprets the
instruction and processes the data contained in computer programs:
a. MU
b. ALU
c.
CPU
d. PC
97. Which part
work as a the brain of the computer and performs most of the calculation:
a. MU
b. PC
c. ALU
d.
CPU
98. Which is
the main function of the computer:
a. Execute
of programs
b.
Execution of
programs
c. Both
d. None
of these
99. How many
major component make up the CPU:
a. 4
b.
3
c. 6
d. 8
100.
Which register holds the current instruction to be
executed:
a.
Instruction
register
b. Program
register
c. Control
register
d. None
of these
101.
Which register holds the next instruction to be
executed:
a. Instruction register
b. Program
register
c.
Program
control register
d. None
of these
102.
Each instruction is also accompanied by a___________:
a. Microprocessor
b.
Microcode
c. Both
d. None
of these
103.
Which are microcomputers commonly used for commercial
data processing, desktop publishing and engineering application:
a. Digital
computer
b.
Personal
computer
c. Both
d. None
of these
104.
Which microprocessor has the control unit, memory unit
and arithmetic and logic unit:
a.
Pentium IV
processor
b. Pentium
V processor
c. Pentium
III processor
d. None
of these
105.
The processing speed of a computer depends on the
__________of the system:
a.
Clock speed
b. Motorola
c. Cyrix
d. None
of these
106.
Which microprocessor is available with a clock speed of
1.6 GHZ:
a. Pentium
III
b. Pentium
II
c.
Pentium IV
d. All
of these
107.
Which processor are used in the most personal computer:
a.
Intel
corporation’s Pentium
b. Motorola
corporation’s
c. Both
d. None
of these
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