1. Which
is a type of microprocessor that is designed with limited number of
instructions:
a. CPU
b.
RISC
c. ALU
d. MUX
2. Which
unit is a pipeline system helps in speeding up processing over a non pipeline
system:
a.
CPU
b. RISC
c. ALU
d. MUX
3. The
group of binary bits assigned to perform a specified operation is known as:
a. Stack
register
b.
Control word
c. Both
d. None
4. How
many binary selection inputs in the control word:
a. 1
b. 7
c.
14
d. 28
5. In
control word three fields contain how many bits:
a. 1
b. 2
c.
3
d. 4
6. Three
fields contains three bits each so one filed has how many bits in control word:
a. 2
b. 4
c.
5
d. 6
7. How
is selects the register that receives the information from the output bus:
a.
Decoder
b. Encoder
c. MUX
d. All
of these
8. A
bus organization for seven _____register:
a. ALU
b. RISC
c.
CPU
d. MUX
9. How
many source register propagate through the multiplexers:
a. 1
b.
2
c. 3
d. 4
10. How many
bits of OPR select one of the operations in the ALU:
a. 2
b. 3
c. 4
d.
5
11. five bits
of OPR select one of the operation in the ____ in control register:
a. CPU
b. RISC
c.
ALU
d. MUX
12. The OPR
field has how many bits:
a. 2
b. 3
c. 4
d.
5
13. In stack
organization the insertion operation is known as ____:
a. Pop
b.
Push
c. Both
d. None
14. In stack
organization the deletion operation is known as ____:
a.
Pop
b. Push
c. Both
d. None
15. A stack in
a digital computer is a part of the_____:
a. ALU
b. CPU
c.
Memory unit
d. None
of these
16. In stack
organization address register is known as the:
a. Memory
stack
b.
Stack
pointer
c. Push
operation
d. Pop
operation
17. In register
stack a stack can be organized by a ______number of register:
a. Infinite
number
b.
Finite
number
c. Both
d. None
18. Which
operation are done by increment or decrement the stack pointer:
a. Push
b. Pop
c.
Both
d. None
19. In register stack a stack can be a finite
number of_____:
a. Control
word
b.
Memory word
c. Transfer
word
d. All
of these
20. The stack
pointer contains the address of the word that is currently on____:
a.
Top of the
stack
b. Down
of the stack
c. Top
and Down both
d. None
21. In register
stack items are removed from the stack by using the ____operation:
a. Push
b.
Pop
c. Both
d. None
22. Which
register holds the item that is to be written into the stack or read out of the
stack:
a. SR
b. IR
c. RR
d.
DR
23. In register
stack the top item is read from the stack into:
a. SR
b. IR
c. RR
d.
DR
24. In
conversion to reverse polish notation the ____and____ operations are performed
at the end:
a.
Add and
subtract
b. Subtract
and multiplication
c. Multiplication
and subtract
d. All
of these
25. RPN stands
for:
a.
Reverse
polish notation
b. Read
polish notation
c. Random
polish notation
d. None
of these
26. Instruction
formats contains the memory address of the______:
a. Memory
data
b.
Main memory
c. CPU
d. ALU
27. In
instruction formats instruction is represent by a________ of bits:
a.
Sequence
b. Parallel
c. Both
d. None
28. In instruction formats the information
required by the ______ for execution:
a. ALU
b.
CPU
c. RISC
d. DATA
29. The operation
is specified by a binary code known as the_____:
a. Operand
code
b.
Opcode
c. Source
code
d. All
of these
30. Which are
contains one or more register that may
be referenced by machine instruction:
a. Input
b. Output
c.
CPU
d. ALU
31. Memory
–mapped ___is used this is just another memory address:
a. Input
b. Output
c.
Both
d. None
32. Which operation use one operand or unary
operations:
a. Arithmetic
b. Logical
c.
Both
d. None
33. 3-Address
format can be represented as :
a.
dst
<-[src1][src2]
b. dst
->[src1][src2]
c. dst
<->[src1][src2]
d. All
of these
34. 2- Address
format can be represented as:
a. dst
->[dst]*[src]
b.
dst<-[dst]*[src]
c. dst<->[dst]*[src]
d. All
of these
35. In
1-address format how many address is used both as source as well as
destination:
a.
1
b. 2
c. 3
d. 4
36. The stack
pointer is maintained in a____:
a. Data
b.
Register
c. Address
d. None
of these
37. ___ mode of
addressing is a form of implied addressing:
a.
Stack
b. Array
c. Queue
d. Binary
38. Stack uses
RPN to solve ______expression:
a. Logical
b.
Arithmetic
c. Both
d. None
39. In the RPN
scheme the numbers and operators are listed__________:
a.
One after
another
b. One
before another
c. Another
after one
d. Another
before one
40. In
addressing modes instruction has primarily how many components:
a. 1
b.
2
c. 3
d. 4
41. EA stands
for:
a. Effective
add
b. Effective
absolute
c.
Effective
address
d. End
address
42. In which
addressing the operand is actually present in instruction:
a.
Immediate
addressing
b. Direct
addressing
c. Register
addressing
d. None
of these
43. In which addressing the simplest addressing
mode where an operand is fetched from memory is_____:
a. Immediate
addressing
b.
Direct
addressing
c. Register
addressing
d. None
of these
44. which
addressing is a way of direct addressing:
a. Immediate addressing
b. Direct
addressing
c.
Register
addressing
d. None
of these
45. In which
mode the main memory location holds the EA of the operand:
a. Immediate
addressing
b. Direct
addressing
c. Register
addressing
d.
Indirect
addressing
46. Which
addressing is an extremely influential way of addressing:
a.
Displacement
addressing
b. Immediate
addressing
c. Direct
addressing
d. Register
addressing
47. In the base
–register addressing the register reference may be _____:
a. Implicit
b. Explicit
c.
Both
d. None
48. In post
–indexing the indexing is performed_____
a. Before
the indirection
b.
After the
indirection
c. Same
time indirection
d. All
of these
49. In
post-indexing the contents of the address field are used to access a memory
location containing a___ address:
a. Immediate
addressing
b.
Direct
addressing
c. Register
addressing
d. None
of these
50. In pre
–indexing the indexing is performed_____
a.
Before the
indirection
b. After
the indirection
c. Same
time indirection
d. All
of these
51. The final
addressing mode that we consider is______:
a. Immediate
addressing
b. Direct
addressing
c. Register
addressing
d.
Stack
addressing
52. In data
transfer manipulation designing as instruction set for a system is a
complex_____ :
a.
Art
b. System
c. Computer
d. None
of these
53. Which addressing is an extremely influential
way of addressing:
a. Immediate addressing
b. Direct
addressing
c. Register
addressing
d.
Displacement
addressing
54. Which
addressing offset can be the content of PC and also can be negative:
a.
Relative
addressing
b. Immediate
addressing
c. Direct
addressing
d. Register
addressing
55. The length
of instruction set depends on:
a. Data
size
b.
Memory size
c. Both
d. None
56. In length
instruction some programs wants a complex instruction set containing more
instruction, more addressing modes and greater address rang, as in case
of_____:
a. RISC
b.
CISC
c. Both
d. None
57. In length instruction other programs on the
other hand, want a small and fixed-size instruction set that contains only a
limited number of opcodes, as in case of_____:
a.
RISC
b. CISC
c. Both
d. None
58. The
instruction set can have variable-length instruction format primarily due to:
a. Varying
number of operands
b. Varying
length of opcodes in some CPU
c.
Both
d. None
59. An
instruction code must specify the address of the____:
a. Opecode
b.
Operand
c. Both
d. None
60. A simple
____ differs widely from a Turing machine:
a. CISC
b. RISC
c.
CPU
d. ALU
61. How many types of basically Data
manipulation:
a. 1
b. 2
c.
3
d. 4
e.
62. Which is
data manipulation types are:
a. Arithmetic
instruction
b. Shift
instruction
c. Logical
and bit manipulation instructions
d.
All of these
63. Arithmetic
instruction are used to perform operation on:
a.
Numerical
data
b. Non-numerical
data
c. Both
d. None
64. How many
basic arithmetic operation:
a. 1
b. 2
c. 3
d.
4
65. which are
arithmetic operation are:
a. Addition
b. Subtraction
c. Multiplication
d. Division
e.
All of these
f.
None of these
66. In which
instruction are used to perform Boolean operation on non-numerical data:
a.
Logical and
bit manipulation
b. Shift
manipulation
c. Circular
manipulation
d. None
of these
67. Which
operation is used to shift the content of an operand to one or more bits to
provide necessary variation:
a. Logical
and bit manipulation
b.
Shift
manipulation
c. Circular
manipulation
d. None
of these
68. ________is
just like a circular array:
a. Data
b.
Register
c. ALU
d. CPU
69. Which
control refers to the track of the address of instructions:
a. Data
control
b. Register
control
c.
Program
control
d. None
of these
70. In program
control the instruction is set for the statement in a:
a. Parallel
b.
Sequence
c. Both
d. None
71. How many
types of unconditional jumps used in program control are follows:
a. 1
b. 2
c.
3
d. 4
72. Which are unconditional jumps used in program
control are follows:
a. Short
jump
b. Near
jump
c. Far
jump
d.
All of these
73. Which
instruction is used in program control and used to decrement CX and conditional
jump:
a.
Loop
b. Shift
manipulation
c. Circular
manipulation
d. None
of these
74. Which is
always considered as short jumps:
a.
Conditional
jump
b. Short
jump
c. Near
jump
d. Far
jump
75. Who change
the address in the program counter and cause the flow of control to be altered:
a. Shift
manipulation
b. Circular
manipulation
c.
Program
control instruction
d. All
of these
76. Which is
the common program control instructions are:
a. Branch
b. Jump
c. Call
a subroutine
d. Return
e.
All of these
f.
None of these
77. Which is a
type of microprocessor that is designed with limited number of instructions:
a. CISC
b. RISC
c.
Both
d. None
78. SMP Stands for:
a. System
multiprocessor
b.
Symmetric
multiprocessor
c. Both
d. None
79. UMA stands
for:
a.
Uniform
memory access
b. Unit
memory access
c. Both
d. None
80. NUMA stands
for:
a.
Number
Uniform memory access
b. Not
Uniform memory access
c. Non
Uniform memory access
d. All
of these
81. SIMD stands
for:
a. System
instruction multiple data
b.
Single instruction
multiple data
c. Symmetric
instruction multiple data
d. Scale
instruction multiple data
82. MIMD stands
for:
a. Multiple
input multiple data
b. Memory
input multiple data
c.
Multiple
instruction multiple data
d. Memory
instruction multiple data
83. HLL stands
for:
a.
High level
languages
b. High
level line
c. High
level logic
d. High
level limit
84. Which is a
method of decomposing a sequential process into sub operations:
a.
Pipeline
b. CISC
c. RISC
d. Database
85. How many
types of array processor:
a. 1
b.
2
c. 3
d. 4
86. Which are
the types of array processor:
a. Attached
array processor
b. SIMD
array processor
c.
Both
d. None
87. Which are
the application of vector processing:
a. Weather
forecasting
b. Artificial
intelligence
c. Experts
system
d. Images
processing
e. Seismology
f.
Gene mapping
g. Aerodynamics
h.
All of these
i.
None of these
88. Which types
of jump keeps a 2_byte instruction that holds the range from- 128to127 bytes in
the memory location:
a. Far jump
b. Near jump
c.
Short jump
d. All
of these
89. Which types of register holds a single vector
containing at least two read ports and one write ports:
a. Data
system
b. Data
base
c. Memory
d.
Vector
register
90. Parallel
computing means doing several takes simultaneously thus improving the
performance of the________:
a. Data
system
b.
Computer
system
c. Memory
d. Vector
register
91. Which is
used to speed-up the processing:
a. Pipeline
b. Vector
processing
c.
Both
d. None
92. Which
processor is a peripheral device attached to a computer so that the performance
of a computer can be improved for numerical computations:
a.
Attached
array processor
b. SIMD
array processor
c. Both
d. None
93. Which
processor has a single instruction multiple data stream organization that
manipulates the common instruction by means of multiple functional units:
a. Attached
array processor
b.
SIMD array
processor
c. Both
d. None
94. Which carry
is similar to rotate without carry operations:
a. Rotate
carry
b.
Rotate
through carry
c. Both
d. None
95. In the case
of a left arithmetic shift , zeros are Shifted to the ______:
a. Left
b.
Right
c. Up
d. Down
96. In the case
of a right arithmetic shift the sign bit values are shifted to the_____:
a.
Left
b. Right
c. Up
d. Down
1.c
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