1. _______is
the first step in the evolution of programming
languages:
a. machine
language
b.
assembly
language
c. code
language
d. none
of these
2. Mnemonic
refers to:
a. Instructions
b. Code
c.
Symbolic
codes
d. Assembler
3. Mnemonic
represent:
a.
Operation
codes
b. Strings
c. Address
d. None
of these
4. To
represent addresses in assembly language we use:
a.
String
characters
b. Arrays
c. Structure
d. Enum
5. Assembler
works to convert assembly language program into machine language :
a.
Before the
computer can execute it
b. After
the computer can execute it
c. In
between execution
d. All
of these
6. ________generation
computers use assembly language:
a. First
generation
b. Third
generation
c.
second
generation
d. fourth
generation
7. Assembly
language program is called:
a. Object
program
b.
Source
program
c. Oriented
program
d. All
of these
8. To
invoke assembler following command are given at command line:
a. $
hello.s -o hello.o
b. $as
hello.s –o o
c. $
as hello –o hello.o
d.
$ as hello.s
–o hello.o
9. By
whom address of external function in the assembly source file supplied by
______ when activated:
a. Assembler
b.
Linker
c. Machine
d. Code
10. An______ -o
option is used for:
a. Input
file
b. External
file
c.
Output file
d. None
of these
11. The
assembler translates ismorphically______ mapping from mnemonic in these
statements to machine instructions:
a.
1:1
b. 2:1
c. 3:3
d. 4:1
12. Assembler
works in______ phases:
a. 1
b. 3
c.
2
d. 4
13. The assembler
in first pass reads the program to collect
symbols defined with offsets in a table_______:
a. Hash
table
b.
Symbol table
c. Both
a& b
d. None
of these
14. In second
pass, assembler creates _______in binary format for every instruction in
program and then refers to the symbol table to giving every symbol an______
relating the segment.
a. Code
and program
b. Program
and instruction
c.
Code and
offset
d. All
of these
15. which of
the 2 files are created by the assembler:
a.
List and
object file
b. Link
and object file
c. Both
a & b
d. None
of these
16. In which
code is object file is coded:
a. Link
code
b. Decimal
code
c. Assembly
code
d.
Binary code
17. which type
of errors are detected by the assembler:
a.
syntax error
b. logical
error
c. run
time error
d. none
of these
18. MOVE AX BX
in this LINES OF CODE what type of error is declared:
a.
Undeclared
identifier MOVE
b. undeclared
identifier AX
c. Accept
as a command
d. Not
look in symbol table
19. In
given lines of code MOV AX,BL have
different type of operands according to
assembler for 8086 architecture these identifiers must be of:
a. Different
type only in byte
b.
Same type
either in word or byte
c. Both
a & b
d. None
of these
20. What type
of errors are not detected by assemblers:
a. Syntax
error
b. Run
time error
c.
Logical
error
d. All
of these
21. ______serves
as the purpose of documentation only:
a.
List
b. object
c. link
d. code
22. An
assembler is a utility program that performs:
a. Isometric
translation
b.
Isomorphic
translation
c. Isochoric
translation
d. None
of these
23. Assemblers are of 2 types:
a. 1
pass
b. 2
pass
c.
both a &
b
d. none
of these
24. CP/CMS
assembly language was written in ________assembler:
a. S/340
b. S-350
c. S/320
d.
S/360
25. ASM-H widely used _____assembler:
a.
S/370
b. S/380
c. S/390
d. S/360
26. Assembler
is a_______:
a. Interpreter
b.
Translator
c. Exchanger
d. None
of these
27. A_______
processor controls repetitious writing of sequence:
a.
Macro
b. Micro
c. Nano
d. All
of these
28. IBM-360
type language is example which supporting______ language:
a. Micro
b.
Macro
c. Both
a & b
d. None
of these
29. _________
is attached to using macro instruction definition:
a.
Name
b. Definition
c. Identifier
d. All
of these
30. END of
macro definition by:
a. NAME
b.
MEND
c. DATA
d. MEMORY
31. Process of
replacing the sequence of lines of codes is known as:
a.
Expanding
die macro
b. Expanding
tri macro
c. Tetra
macro
d. None
of these
32. A program
that links several programs is called:
a.
Linker
b. Loader
c. Translator
d. None
of these
33. _______address
is not assigned by linker:
a.
Absolute
b. Relative
c. Both
a & b
d. None
of these
34. ________address
is provided by linker to modules linked together that starting from______:
a. Absolute
and 0
b.
Relative and
0
c. Relative
and 1
d. Relative
and 3
35. A linker is
also known as:
a. Binder
b. Linkage
editor
c.
Both a &
b
d. None
of these
36. Loading is
_______ with the task of storage management of operating system and mostly
preformed after assembly:
a.
Bound
b. Expanded
c. Overlaps
d. All
of these
37. _______contain
library program have to be indicated to the loader:
a.
Externally
defined
b. Internally
defined
c. Executable
file
d. All
of these
38. It is the
task of the ________to locate externally defined symbols in programs, load them
in to memory by placing their _______of symbols in calling program:
a. Loader
and name
b. Linker
and values
c. Linker
and name
d.
Loader and
values
39. Linker
creates a link file containing binary codes and also produces_______ containing
address information on linked files:
a.
Link map
b. Map
table
c. Symbol
map
d. None
of these
40. how many
types of entities contained by assembler to handle program:
a. 4
b. 2
c.
3
d. 5
41. which of
the following are types of assembler entities:
a. Absolute
entities
b. Relative
entities
c. Object
program
d.
All of these
42. ________have
addresses where instructions are stored along with address of working storage:
a.
Relative
entities
b. Absolute
entities
c. Both
a & b
d. None
of these
43. Absolute
entities are __________whom value signify storage locations that are
independent of resulting machine code:
a. Numeric
constants
b. String
constants
c. Fixed
addresses
d. Operation
codes
e.
All of these
44. A module
contains machine code with specification on______:
a.
Relative
addresses
b. Absolute
addresses
c. Object
program
d. None
of these
45. After
actual locations for main storage are known, a ______adjusts relative addresses
to these actual locations:
a.
Relocating
loader
b. Locating
loader
c. Default
loader
d. None
of these
46. If there is
a module from single source-language only that does not contain any external
references, it doesn’t need a linker to load it and is loaded______:
a. Indirectly
b.
Directly
c. Extending
d. None
of these
47. Modern
assemblers for RISC based architectures make optimization of instruction
scheduling to make use of CPU _______efficiently:
a.
Pipeline
b. Without
pipeline
c. Both
a & b
d. None
of these
48. which are
of the following modern assemblers:
a. MIPS
b. Sun
SPARC
c. HP
PA-RISC
d. x86(x64)
e.
all of these
49. How many
types of loop control structures in C language:
a. 4
b. 5
c. 2
d.
3
50. Types of
loop control statements are:
a. For
loop
b. While
loop
c. Do-while
loop
d.
All of these
51. <Initial
value> is_______ which initializes the value of variable:
a.
Assignment
expression
b. Condition
value
c. Increment/decrement
d. None
of these
52. The format
“%8d” is used to print_______ values in a line:
a. 11
b.
10
c. 9
d. 12
53. <Condition>
is a _________expression which will have value true or false:
a. Relational
b. Logical
c.
Both a &
b
d. None
of these
54. <Increment> is the________ value of
variable which will be added every time:
a.
Increment
b. Decrement
c. Expanding
d. None
of these
55. _______is
the statement block of for loop lies inside block of another for loop:
a.
Nested for
loop
b. Nested
while loop
c. Nested
do-while loop
d. None
of these
56. SPARC
stands for:
a. Scalable
programmer architecture
b.
Scalable
processor architecture
c. Scalable
point architecture
d. None
of these
57. Full form
of MIPS assembler is:
a.
Microprocessor
without interlocked pipeline stage
b. Microprocessor
with interlocked pipeline stage
c. Both
a & b
d. None
of these
58. _______
statement block is executed atleast once for any value of the condition:
a. For
statement
b.
Do-while
statement
c. While
statement
d. None
of these
59. _______statement is an unconditional transfer of control statement:
a.
Goto
b. Continue
c. Switch
d. All
of these
60. In Goto
statement the place to which control is transferred is identified by a
statement______:
a.
Label
b. Display
c. Break
d. None
of these
61. The
continue statement is used to transfer the control to the________ of a statement
block in a loop:
a. End
b.
Beginning
c. Middle
d. None
of these
62. The__________
statement is used to transfer the control to the end of statement block in a
loop:
a. Continue
b.
Break
c. Switch
d. Goto
63. ________function
is used to transfer the control to end of a program which uses one argument( )
and takes value is zero for_______ termination and non-zero for
_______termination:
a.
Exit(
),normal, abnormal
b. Break,
normal, abnormal
c. Both
a & b
d. None
of these
64. To design a
program it requires_______:
a.
Program
specification
b. Code
specification
c. Instruction
specification
d. Problem
specification
65. Testing
helps to ensure _______of the program for use within a system:
a. Quality,
accuracy and except
b.
Quality,
accuracy and acceptance
c. Design,
assurance and acceptance
d. Quality,
accuracy and development
66. An
unstructured program uses a ________ approach to solve problems:
a. Linear
b. Top
down
c.
Both a &
b
d. None
of these
67. In a
complex program, the ______overlaps:
a.
Branching
b. Condition
c. Both
a & b
d. None
of these
68. How many
structures structured programs are written:
a.
3
b. 2
c. 1
d. 6
69. following
are structured programs written in simple structures:
a. Sequence
b. Selection
c. Iteration
d.
All of these
70. Iteration also called:
a.
Repetition
b. Straight
c. Selection
d. Sequence
71. In
________instructions are followed one after the other in the preset order in
which they appear within program:
a.
Sequence
b. Selection
c. Break
d. Iteration
72. _______means
that one of two alternative sequences of instruction is chosen based on logical
condition:
a. Sequence
b.
Selection
c. Repetition
d. None
of these
73. _________is
sequence of instructions is executed and repeated any no. of times in loop
until logical condition is true:
a. Iteration
b. Repetition
c.
Both a &
b
d. None
of these
74. A
________is a small program tested separately before combining with final
program:
a.
Module
b. Block
c. selection
d. none
of these
75. _______uses
various symbols to represent function
within program and is _______representation:
a.
Flowchart,
pictorial
b. Algorithm,
pictorial
c. Pictorial,
flowchart
d. None
of these
76. ______Avoid
crossing flow lines:
a.
Flowchart
b. Algorithm
c. Both
a & b
d. None
of these
77. A flow
chart is drawn from top to bottom and_____:
a. Right
to left
b. Only
right
c.
Left to
right
d. Only
left
78. Flowchart that exceed page should be properly
linked using ________to portions of flowchart
on different pages:
a.
Connectors
b. Interconnections
c. Connections
d. None
of these
79. ________is
useful to prepare detailed program documentation:
a.
Flowchart
b. Algorithm
c. Both
a & b
d. None
of these
80. Pseudo
means:
a.
Imitation
b. Imitate
c. In
imitation
d. None
of these
81. Preparing
the pseudocode requires _______time than drawing flowchart:
a.
Less
b. More
c. Optimum
d. None
of these
82. There is
_____standard for preparing pseudocode instructions:
a.
No
b. 4
c. 2
d. 6
83. ______are
used to translate high level language instructions to a machine code:
a. Translators
b. Interpreters
c.
Compilers
d. None
of these
84. The
compiler _______translate a program code
with any syntax error:
a. Can
b.
Cannot
c. Without
d. None
of these
85. Before
checking the program for errors in translating code into machine language the
high level language code is loaded into_________:
a. Register
b.
Memory
c. Data
d. CPU
86. After
compilation of the program ,the operating system of computer activates:
a. Loader
b.
Linker
c. Compiler
d. None
of these
87. The linker
has utilities needed for ________within the translated program:
a. Input
b. Output
c. Processing
d.
All of these
88. Flowchart
is a_______ representation of an algorithm:
a. Symbolic
b. Diagrammatic
c.
Both a &
b
d. None
of these
89. In flow
chart symbols the _______operation represents the direction of flow:
a. Connector
b. Looping
c.
Arrows
d. Decision
making
90. Which
register is memory pointer:
a.
Program
counter
b. Instruction
register
c. Stack
pointer
d. Source
index
91. How many
approaches are used to design control unit:
a.
2
b. 3
c. 4
d. 5
92. Which are
the following approaches used to design control unit:
a. Hardwired
control
b. Microprogrammed
control
c.
Both a &
b
d. None
of these
93. Cache
memory is located between main memory and_____:
a.
CPU
b. Memory
c. Both
a & b
d. None
of these
e.
94. _______arrow
represents the value obtained by evaluating right side expression/variable to
the left side variable:
a. Forth
b. Inbetween
c.
Back
d. None
of these
95. A ________
is written as separate unit, apart from main and called whenever necessary:
a.
Subroutine
b. Code
c. Block
d. None
of these
96. _______uses
the stack to store return address of subroutine:
a. CPU
b.
Microprocessor
c. register
d. memory
97. A
subroutine is implemented with 2 associated instructions:
a. CALL
b. RETURN
c.
Both a &
b
d. None
of these
98. Call
instruction is written in the ______program:
a.
Main
b. Procedures
c. Program
d. Memory
99. Return
instruction is written in_______ to written to main program:
a.
Subroutine
b. Main
program
c. Both
a & b
d. None
of these
100.
When subroutine is called contents of program counter
is location address of _______instruction following call instruction is stored
on ________and program execution is transferred to______ address:
a. Non
executable, pointer and subroutine
b. Executable,
Stack and Main program
c. Executable, Queue and Subroutine
d.
Executable,
Stack and Subroutine
101.
A subroutine called by another subroutine is called:
a.
Nested
b. For
loop
c. Break
d. Continue
102.
The extent nesting in subroutine is limited only by:
a.
Number of
available Stack locations
b. Number
of available Addressing locations
c. Number
of available CPU locations
d. Number
of available Memory locations
103.
Which are of the following instructions of hardware
subroutines:
a. SCAL
b. SXIT
c.
Both a &
b
d. None
of these
104.
Importance in
local variable and index registers in subroutine does_____:
a. Alter
b.
Not alter
c. Both
a & b
d. None
of these
105.
Markers in subroutine cannot be accepted as limits
whereas this markers stands for:
a.
Top of stack
b. Bottom
of stack
c. Middle
of stack
d. All
of these
106.
Subroutines are placed in identical section to caller
so that SCAL and SXIT _______overpass divison limits:
a.
Don’t
b. Does
c. Cross
d. By
107.
_________subroutine declaration come after procedure announcement:
a.
Global
b. Local
c. Both
a & b
d. None
of these
108.
subroutines are invoked by using their________ in a
subroutine call statement and replacing formal parameters with________
parameters:
a. Identifier
and formal
b.
Identifier
and actual
c. Expression
and arguments
d. None
of these
109.
Parameters can be stacked by ________just as with
procedures:
a.
Asterisk(*)
b. Arrow
c. Line
d. Pipeline
110.
The subroutines are determined by functioning of
________instructions:
a.
SCAL and SXIT
b. only
SCAL
c. only
SXIT
d. none
of these
111.
Call is________ subroutine call:
a. Conditional
b.
Unconditional
c. Both
a & b
d. None
of these
112.
A flag is a _________that keep track of a changing condition
during computer run:
a. Memory
b. Register
c. Controller
d. None
of these
113.
When a subroutine is ________the parameters are loaded
onto the stack and SCAL is executed:
a. Executed
b.
Invoked
c. Ended
d. Started
114.
Subroutine is called _______:
a. In
Same program
b. In
external program
c.
Both a &
b
d. None
of these
115.
If internal subroutine is called global data is used to
pass values defining parameters between _________program and defined _______:
a.
Main and subroutine
b. Local
and subroutine
c. Global
and subroutine
d. Global
and main
116.
In what type of
subroutine actual parameters are passed through the main program to formal
parameters in the related subroutine:
a. Internal
b.
External
c. Both
a & b
d. None
of these
117.
By defining the _________register as last in first out
stack the sequence can handle nested subroutines:
a. S
b. J
c.
R
d. T
118.
The ______stack can be 4-word memory addressed by 2 bits from an up/down counter
known as the stack pointer:
a. FIFO
b. PIPO
c. SISO
d.
LIFO
119.
getchar :: IO char in this given function what is
indicated by IO char:
a.
when getchar
is invoked it returns a character
b. when
getchar is executed it returns a character
c. both
a & b
d. none
of these
120.
If we define putchar function in putchar :: char ->
IO ( ) syntax than character input as an argument and returns_____:
a. Useful
value
b. Get
output
c.
Get no
output
d. None of these
121.
The front panel display provides lights as green LED
represent _____ and red LED represent _____for device programmer who writes
input/output basic:
a.
Busy and
Error
b. Error
and Busy
c. Busy
and Busy
d. Error
and Error
122.
The input data for processing uses the standard input
device which by default is a ________:
a. Mouse
b. Scanner
c.
Keyboard
d. Monitor
123.
The processed data is sent for output to standard ________device which
by default is computer screen:
a. Input
b.
Output
c. Both
a & b
d. None
of these
124.
Each instruction is executed by set of micro operations
termed as:
a.
Micro
instructions
b. Mini
instructions
c. Both
a & b
d. None
of these
125.
For each micro operation the control unit generates set
of______ signals:
a.
Control
b. Address
c. Data
d. None
of these
126.
Sequence of microinstructions is termed as micro
program or________:
a. Hardware
b. Software
c.
Firmware
d. None
of these
127.
The micro program is an ________written in microcode
and stored in firmware which is also referred as___________:
a.
Interpreter
and control memory
b. Translator
and control store
c. Translator
and control memory
d. Interpreter
and Translator
128.
Compared to hardware, firmware is ________to design
micro programmed organization:
a. Difficult
b.
Easier
c. Both
a& b
d. None
of these
129.
Compared to software, firmware is _______to write:
a. Easier
b.
Difficult
c. Mediator
d. Optimum
130.
_________program converts machine instructions into
control signals:
a. Control
memory program
b. Control
store program
c.
Both a &
b
d. Only
memory
131.
who coined the term micro program in 1951:
a. T.V.
Wilkes
b.
M.V. Wilkes
c. S.V.
Wilkes
d. D.V.
Wilkes
132.
what is full form of EDSAC:
a. Electronic
delay source accumulator calculator
b. Electronic
delay storage automatic code
c. Electronic
destination source automatic calculator
d.
Electronic
delay storage automatic calculator
133.
Who led to development of read –only magnetic core matrix
for use in control unit of small computer at IBM’s laboratory:
a.
John
Fairclough’s
b. Johny
fairclough
c. Mr.
Redcliff
d. M.V.
Wilkes
134.
From1961-1964 John fairclough’s research played an
important role to pursue full range of compatible computers as system:
a.
System/360
b. System/460
c. System/560
d. System/780
135.
Each microinstructions cycle is made of 2 parts:
a. Fetch
b. Execute
c. Code
d.
Both a &
b
136.
One of use of microprogramming to implement ________ of
processor in Intel 80x86 and Motorola 680x0 processors whose instruction set
are evolved from 360 original:
a. Control
structure
b. Without
control
c.
Control unit
d. Only
control
137.
The function of these microinstructions is to issue the
micro orders to______:
a.
CPU
b. Memory
c. Register
d. Accumulator
138.
Micro-orders generate the_______ address of operand and execute instruction and
prepare for fetching next instruction from the main memory:
a. Physical
b.
Effective
c. Logical
d. all
of above
139.
Which of the following 2 task are performed to execute
an instruction by MCU:
a. Microinstruction
execution
b. Microinstruction
sequencing
c.
Both a &
b
d. None
of these
140.
What is the purpose of microinstruction executions:
a. Generate
a control signal
b. Generate
a control signal to compile
c.
Generate a
control signal to execute
d. All
of these
141.
Which microinstruction provide next instruction from
control memory:
a. Microinstruction
execution
b. Microinstruction
Buffer
c. Microinstruction
decoder
d.
Microinstruction
Sequencing
142.
Which are the following components of microprogramed
units to implement control process:
a. Instruction
register
b. Microinstruction
address generation
c. Control
store microprogram memory
d. Microinstruction
Buffer
e. Microinstruction
decoder
f.
All of these
143.
Microcodes are stored as firmware in _______:
a.
Memory chips
b. Registers
c. accumulators
d. none
of these
144.
A control memory is______ stored in some area of
memory:
a.
Control
instruction
b. Memory
instruction
c. Register
instruction
d. None
of these
145.
A computer having writable control memory is known as_________:
a. Static
micro programmable
b.
Dynamic
micro programmable
c. Both
a & b
d. None
of these
146.
The control memory contains a set of words where each
word is:
a.
Microinstruction
b. Program
c. Sets
d. All
of these
147.
During program execution content of main memory undergo
changes and, but control memory has______ microprogram:
a. Static
b. Dynamic
c. Compile
time
d.
Fixed
148.
What happens if computer is started :
a. It
executes “CPU” microprogram which is sequence of microinstructions stored in
ROM
b. It
executes “code” microprogram which is sequence of microinstructions stored in
ROM
c. It executes “boot” microprogram which is
sequence of microinstructions stored in ROM
d. It
executes “strap loader” microprogram which is sequence of microinstructions
stored in ROM
149.
Control memory is part of ______ that has addressable
storage registers and used as temporary storage for data:
a. ROM
b.
RAM
c. CPU
d. Memory
150.
How many modes the address in control memory are
divided:
a.
2
b. 3
c. 5
d. 7
151.
which of the following is interrupt mode:
a. Task
mode
b.
Executive
mode
c. Both
a & b
d. None
of these
152.
Mode of addresses in control memory are:
a. Executive
mode
b. Task
mode
c.
Both a &
b
d. None
of these
153.
Addresses in control memory is made by____ for each
register group:
a.
Address
select logic
b. Data
select logic
c. Control
select logic
d. All
of these
154.
There are how many register groups in control memory:
a. 3
b.
5
c. 6
d. 8
155.
What type of circuit is used by control memory to
interconnect registers:
a.
Data routing circuit
b. Address
routing circuit
c. Control
routing circuit
d. None
of the these
156.
Which memory is used to copy instructions or data
currently used by CPU:
a. Main
memory
b. Secondary
memory
c.
Cache memory
d. None
of these
157.
Copy of instruction in cache memory is known as:
a. Execution
cache
b. Data
cache
c.
Instruction
cache
d. All
of these
158.
Copy of data in cache memory is called:
a.
Data cache
b. Execution
cache
c. Address
cache
d. Control
cache
159.
What are 2 advantages of cache memory:
a. Reduction
of average access time for CPU memory
b. Reduction
of bandwidth of available memory of CPU
c.
Both a &
b
d. None
of these
160.
On what method search in cache memory used by the
system:
a. Cache
directing
b.
Cache
mapping
c. Cache
controlling
d. Cache
invalidation
161.
______process starts when a cpu with cache refers to a
memory:
a. Main
memory
b. External
memory
c.
Cache
d. All
of these
162.
When cache
process starts hit and miss rate defines in cache directory:
a.
during
search reads
b. during
search writes
c. during
replace writes
d. during
finding writes
163.
In cache memory hit rate indicates:
a. Data
from requested address is not available
b.
Data from
requested address is available
c. Control
from requested address is available
d. Address
from requested address is not available
164.
In cache memory miss rate indicates:
a. Availability
of requested data
b. Availability
of requested address
c.
Non-Availability
of requested data
d. Non-Availability
of requested address
165.
Which 3 areas are used by cache process:
a.
Search,
updating, invalidation
b. Write,
updating, invalidation
c. Search,
read, updating
d. Invalidation,
updating, requesting
166.
Updating writes to cache data and also to _______:
a.
Directories
b. Memory
c. Registers
d. Folders
167.
Invalidation writes only to_____ and erases previously
residing address in memory:
a. Folders
b. Memory
c.
Directory
d. Files
168.
_______machine instruction creates branching to some
specified location in main memory if result of last ALU operation is Zero or
Zero flag is set:
a. Branch
on One
b. Branch
on Three
c. Branch
on Nine
d.
Branch on
Zero
169.
Full form of CAR:
a.
Control
address register
b. Content
address register
c. Condition
accumulator resource
d. Code
address register
170.
Two types of microinstructions are:
a. Branching
b. Non-branching
c.
Both a &
b
d. None
of these
171.
Which are 3 ways to determine address of next micro
instruction to be executed:
a. Next
sequential address
b. Branching
c. Interrupt
testing
d.
All of these
172.
Branching can be________:
a. Conditional
b. Unconditional
c.
Both a &
b
d. None
of these
173.
In which branching condition is tested which is
determined by status bit of ALU:
a. Unconditional
b.
Conditional
c. Both
a & b
d. None
of these
174.
which branch is
achieved by fixing status bit that output of multiplexer is always one:
a.
Unconditional
b. Conditional
c. Looping
d. All
of these
175.
Which register is used to store addresses of control
memory from where instruction is fetched:
a. MAR
b. BAR
c.
CAR
d. DAR
176.
Control ROM is the control memory that holds:
a.
Control
words
b. Memory
words
c. Multiplexers
d. Decoders
177.
Opcode is the
machine instruction obtained from decoding instruction stored in:
a. Stack
pointer
b. Address
pointer
c.
Instruction
register
d. Incrementer
178.
Branch logic determines which should be adopted to
select the next______ value among possibilities:
a.
CAR
b. GAR
c. HAR
d. TAR
179.
________ generates CAR+1 as possibility of next CAR
value:
a. Decrementer
b.
Incrementer
c. Postfix
d. Prefix
180.
________used to hold return address for operations of
subroutine call branch:
a. TBR
b. HDR
c. SDR
d.
SBR
181.
Which of following 2 types of computer system
considered by micro programmed unit:
a. Micro
level computers
b. Machine
level computers
c.
Both a &
b
d. None
of these
182.
Following are the components of micro programmed
control unit:
a. Subroutine
register
b. Control
address register
c. Memory
Of 128 words with 20 bits per words
d.
All of these
183.
Various machine level components are:
a. Address
register
b. Program
counter
c. Data
register
d. Accumulator
register
e. Memory
of 2K,16 bits/word RAM
f.
Multiplexers
g.
All of these
184.
Data transfers are done using:
a.
Multiplexer
switching
b. Demultiplexer
switching
c. Adder
switching
d. Subtractor
switching
185.
PC can be loaded
from_____:
a. BR
b. CR
c.
AR
d. TR
186.
Which functions are performed by CU:
a. Data
exchange b/w CPU and memory or I/O modules
b. External
operations
c. Internal
operations inside CPU
d.
Both a &
c
187.
Which are internal operations inside CPU:
a. Data
transfer b/w registers
b. Instructing
ALU to operate data
c. Regulation
of other internal operations
d.
All of these
188.
How many paths taken by movement of data in CU:
a. 3
b. 4
c. 5
d.
2
189.
2 data paths in CU are:
a. Internal
data paths
b. External
data paths
c.
Both a &
b
d. None
of these
190.
_______is the data paths link CPU registers with memory
or I/O modules:
a.
External
data paths
b. Internal
data paths
c. Boreal
data paths
d. Exchange
data paths
191.
______is data paths there is movement of data from one
register to another or b/w ALU and a register:
a. External
b. Boreal
c.
Internal
d. Exchange
192.
Which is the input of control unit:
a. Master
clock signal
b. Instruction
register
c. Flags
d. Control
signals from bus
e.
All of these
193.
If _______flag is set then control unit issues control
signals that causes program counter to be incremented by 1:
a.
Zero
b. One
c. Three
d. Eight
194.
Which control unit is implemented as combinational
circuit in the hardware:
a. Microprogrammed
control unit
b.
Hardwired
control unit
c. Blockprogrammed
control unit
d. Macroprogrammed
control unit
195.
Microprograms are usually stored in:
a.
ROM
b. RAM
c. SAM
d. SAN
196.
Among them which is the faster control unit:
a.
Hardwired
b. Microprogrammed
c. Both
a & b
d. None
of these
197.
For CISC architecture_______ controllers are better:
a.
Microprogrammed
b. Hardwired
c. Betterwired
d. None
of these
198.
Full form of FSM is:
a.
Finite state
machine
b. Fix
state machine
c. Fun
source metal
d. All
of these
199.
Rules of FSM are encoded in:
a. ROM
b. Random
logic
c. Programmable
logic array
d.
All of these
200.
In RISC architecture access to registers is made as a
block and register file in a particular register can be selected by using:
a. Multiplexer
b.
Decoder
c. Subtractor
d. Adder
201.
Outputs of instruction/data path in CU are:
a. Reg
R/W
b. Load/Reg-Reg
c. ALU
function select
d. Load
control
e. Read
control
f.
IR Latch
g. JUMP/Branch/Next
PC
h.
All of these
202.
One last bit of control output is for control of_______
state:
a. Minor
b.
Major
c. Mixer
d. None
of these
203.
Following are 4 major states for ‘load’ are:
a. Fetch
b. Decode
c. Memory
d. Write
back
e.
All of these
204.
Jump has 3 major states are:
a. Fetch
b. Decode
c. Complete
d.
All of these
205.
________ state keeps track of position related to
execution of an instruction:
a.
Major
b. Minor
c. Both
a & b
d. None
of these
206.
An instruction always starts with state___:
a. 1
b. 2
c. 3
d.
0
207.
Decoding of an
instruction in RISC architecture means decision on working of control unit for:
a.
Remainder of
instructions
b. Divisor
of instructions
c. Dividend
of instructions
d. None
of these
208.
Which control is used during starting of instruction
cycle:
a. Write
b.
Read
c. R/W
d. None
of these
209.
________function select takes op code in IR translating
to function of ALU and it may be compact binary code or one line per ALU:
a.
ALU
b. CPU
c. Memory
d. Cache
210.
________is dependent on instruction type in CU:
a. Jump
b. Branch
c. NextPC
d.
All of these
211.
__________dependent on instruction and major state and
also comes in starting of data fetch state as well as write back stage in CU:
a. Register
read
b. Register
write
c.
Register R/W
d. All
of these
212.
_______dependence over op-code in CU:
a. Load
register
b.
Load Reg/Reg
c. Only
Load
d. None
of these
213.
Full form of PLA in CU:
a.
Progrmmable
Logic Array
b. Programs
Load Array
c. Programmable
Logic Accumulator
d. all
of these
214.
Which are tasks for execution of CU or MCU:
a. Microinstruction
execution
b. Microinstruction
sequencing
c.
Both a &
b
d. None
of these
215.
Branching is implemented by depending on output of:
a.
CD
b. RG
c. CC
d. CR
216.
Who determine under what conditions the branching will
occur and when:
a. By
combination of CD and BT
b.
By
combination of CD and BR
c. By
combination of CD and CR
d. By
combination of TD and BR
217.
The character U is used to indicate:
a. Undefined
transfers
b. Unfair
transfers
c.
Unconditional
transfers
d. All
of these
218.
Which field is used to requests for branching:
a. DR
b. CR
c. TR
d.
BR
219.
which field is used to determine what type of transfer
occurs:
a.
CR
b. SR
c. BR
d. MR
220.
Source statements consist of 5fields in microinstruction source code are:
a. Lable
b. Micro-ops
c. CD-spec
d. BR-spec
e. Address
f.
All of these
Mee too
ReplyDeleteKya bhai answer to dalte
ReplyDeleteAre bhai jo jyada dark h vhi Answer h
Delete